The Community for Technology Leaders
RSS Icon
Issue No.09 - September (2011 vol.60)
pp: 1313-1326
Mudassar M. Nisar , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
In many DSP applications (image and voice processing), several dBs of SNR loss can be tolerated without noticeable impact on application level performance. For power optimization in such applications, voltage overscaling (VOS) can be used to operate the arithmetic circuitry at or marginally below the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, low cost checksum codes are used for detection and compensation of intermittent errors due to voltage overscaling in linear digital filters. In traditional coding theory, diagnosis of errors is a key problem and incurs significant computation and latency cost. In the proposed approach, low-precision shadow latches are used to identify likely sources of errors due to voltage overscaling to avoid error diagnosis. This allows accurate error compensation with distance-2 checksum codes that are normally good only for error detection but not for correction. Very precise compensation is achieved by distributing the negative of the error value evenly across only the likely erroneous states. This is called guided probabilistic compensation, as compensation is not exact when errors occur simultaneously in more than one state. A feedback controller is used for dynamic voltage overscaling (DVOS) while keeping the error rate in the system within an acceptable range. It is shown that the low cost accurate error compensation allows significant power savings with minimal degradation in system performance (SNR).
Error correcting codes, voltage scaling, guided compensation, low-power filter.
Mudassar M. Nisar, Abhijit Chatterjee, "Guided Probabilistic Checksums for Error Control in Low-Power Digital Filters", IEEE Transactions on Computers, vol.60, no. 9, pp. 1313-1326, September 2011, doi:10.1109/TC.2010.277
[1] P. Shivakumar et al., “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” Proc. Int'l Conf. Dependable System and Networks, pp. 389-398, 2002.
[2] T. Karnik et al., “Scaling Trend of Cosmic Ray Induced Soft Errors in Static Latches beyond 0.18u,” Proc. Symp. VLSI Circuits, pp. 61-62, 2001.
[3] Y.S. Dhillon, A.U. Diril, and A. Chatterjee, “Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits,” Proc. Conf. Design, Automation and Test in Europe, pp. 288-293, 2005.
[4] K.L. Shepard, “Conquering Noise in Deep-Submicron Digital ICs,” IEEE Design and Test of Computers, vol. 15, no. 1, pp. 51-62, Jan.-Mar. 1998.
[5] A.P. Chandrakasan and R.W. Broders, “Minimizing Power Consumption in Digital CMOS Circuits,” Proc. IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
[6] T. Sakurai and A. Richard Newton, “Alpha-Power Law MOSFET Model and Its applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
[7] R. Gonzalez, B.M. Gordon, and M.A. Horowitz, “Supply and Threshold Voltage Scaling for Low Power CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, Aug. 1997.
[8] A. Sinha and A. Chandrakasan, “Energy Efficient Filtering Using Adaptive Precision and Variable Voltage,” Proc. Ann. IEEE Int'l ASIC/SOC Conf., pp. 327-331, 1999.
[9] N.R. Shanbhag, “Reliable and Energy-Efficient Digital Signal Processing,” Proc. Design Automation Conf., pp. 830-835, 2002.
[10] R. Hegde and N. Shanbhag, “A Voltage Overscaled Low-Power Digital Filter IC,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 388-391, Feb. 2004.
[11] B. Shim and N.R. Shanbhag, “Reduced Precision Redundancy for Low-Power Digital Filtering,” Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 148-152, 2001.
[12] L. Wang and N. Shanbhag, “Low-Power Filtering via Adaptive Error-Cancellation,” IEEE Trans. Signal Processing, vol. 51, no. 2, pp. 575-583, Feb. 2003.
[13] J. Choi, B. Shim, A.C. Singer, and N.I. Cho, “Low-Power Filtering via Minimum Power Soft Error Cancellation,” IEEE Trans. Signal Processing, vol. 55, no. 10, pp. 5084-5096, Oct. 2007.
[14] D. Ernst, S. Das, and D. Blaauw, “RAZOR: Circuit-Level Correction of Timing Errors for Low-Power Operation,” IEEE Micro, vol. 24, no. 6, pp. 10-20, Nov./Dec. 2004.
[15] S. Ghosh and K. Roy, “A New Paradigm for Low-Power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '06), pp. 619-624, Nov. 2006.
[16] B.W. Johnson, Design and Analysis of Fault Tolerant Digital System. Addison-Wesley, 1989.
[17] A. Chatterjee and M.A. d'Abreu, “The Design of Fault-Tolerant Linear Digital State Variable System: Theory and Technique,” IEEE Trans. Computers, vol. 42, no. 7, pp. 794-808, July 1993.
[18] V.S. Nair and J.A. Abraham, “Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays,” IEEE Trans. Computers, vol. 39, no. 4, pp. 426-435, Apr. 1990.
[19] J. Jou and J.A. Abraham, “Fault-Tolerant Matrix Arithmetic and Signal Processing on Highly Concurrent Computing Structures,” Proc. IEEE, vol. 74, no. 5, pp. 732-741, May 1986
[20] M. Ashouei et al., “Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study,” Proc. European Test Symp., pp. 35-42, 2006.
[21] M.M. Nisar and M. Ashouei, “Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums,” Proc. IEEE Int'l On-Line Testing Symp. (IOLTS), pp. 173-182, 2007.
[22] R. Burch, F. Najm, P. Yang, and T. Trick, “McPOWER: A Monte Carlo Approach to Power Estimation,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 90-97, Nov. 1992.
[23] J.G. Ziegler and N.B. Nichols, “Optimum Settings for Automatic Controllers,” Trans. Am. Soc. of Mechanical Engineers, vol. 64, pp. 759-768, 1942.
[24] B. Sahu and G.A. Rincón-Mora, “A High-Efficiency Linear RF Power Amplifier with a Power-Tracking Dynamically Adaptive Buck-Boost Supply,” IEEE Trans. Microwave Theory and Techniques, vol. 52, no. 1, pp. 112-120, Jan. 2004.
19 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool