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Issue No.06 - June (2011 vol.60)
pp: 767-782
Yi-Jung Chen , National Taiwan University, Taipei
Chia-Lin Yang , National Taiwan University, Taipei
Jaw-Wei Chi , National Taiwan University, Taipei
Jian-Jia Chen , Karlsruhe Institute of Technology (KIT), Germany
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Existing leakage reduction techniques for hard real-time systems utilize slack to turn off a CPU completely. However, turning on/off a processor involves high performance and energy overheads. Hence, a hard real-time system is very likely to have unutilized slack if only the CPU shutdown technique is used to reduce leakage. Architectural-level shutdown techniques in all instances have a much lower overheads than turning off a CPU; therefore, they can be utilized in a hard real-time system to further reduce CPU leakage. However, existing architecture-level shutdown techniques cause unpredictable performance degradation thereby unsuitable for a hard real-time system that must meet the timing constraint in all cases. This paper is the first attempt to bridge this gap. This paper focuses on cache leakage reduction and proposes the first Timing-Aware Cache Leakage Control (TACLC) mechanism. TACLC exploits system slack to turn cache lines into low-leakage states provided that the timing constraint is met. The experimental results demonstrate that TACLC effectively utilizes system slack to reduce cache leakage. For systems with low CPU utilization, TACLC achieves comparable leakage reduction to the leakage control policy that aggressively turns cache lines into low-leakage modes while neglecting the timing constraint.
Cache, leakage control, hard real-time systems, energy management.
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen, "TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems", IEEE Transactions on Computers, vol.60, no. 6, pp. 767-782, June 2011, doi:10.1109/TC.2011.44
[1] N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, "Leakage Current: Moore's Law Meets Static Power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
[2] J.-J. Chen, H.-R. Hsu, and T.-W. Kuo, "Leakage-Aware Energy-Efficient Scheduling of Real-Time Tasks in Multiprocessor Systems," Proc. IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS), pp. 408-417, 2006.
[3] R. Jejurikar and R. Gupta, "Dynamic Slack Reclamation with Procrastination Scheduling in Real-Time Embedded Systems," Proc. Conf. Design Automation (DAC), pp. 111-116, 2005.
[4] R. Jejurikar, C. Pereira, and R. Gupta, "Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems," Proc. Design Automation Conf. (DAC), pp. 275-280, 2004.
[5] K. Flautner, N.S. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 148-157, 2002.
[6] M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T.N. Vijaykumar, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED), pp. 90-95, 2000.
[7] P. Juang, K. Skadron, M. Martonosi, Z. Hu, D.W. Clark, P.W. Diodato, and S. Kaxiras, "Implementing Branch-Predictor Decay Using Quasi-Static Memory Cells," ACM Trans. Architecture and Code Optimization, vol. 1, pp. 180-219, June 2004.
[8] J.-J. Chen and T.-W. Kuo, "Procrastination Determination for Periodic Real-Time Tasks in Leakage-Aware Dynamic Voltage Scaling Systems," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 289-294, 2007.
[9] "Intel XScale Core Developer Manual," com/design/intelxscale 27347302.pdf, 2011.
[10] S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 240-251, 2001.
[11] M. Paolieri, E. Quinones, F.J. Cazorla, G. Bernat, and M. Valero, "Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems," Proc. 36th Int'l Symp. Compuater Architecture (ISCA), pp. 57-68, 2009.
[12] FreeScale, "Automotive Microcontrollers and Microprocessors," doc/ roadmapBRAUTOPRDCTMAP.pdf , 2011.
[13] A. Davare, Q. Zhu, M.D. Natale, C. Pinello, S. Kanajan, and A. Sangiovanni-Vincentelli, "Period Optimization for Hard Real-Time Distributed Automotive Systems," Proc. 44th Design Automation Conf. (DAC), pp. 278-283, 2007.
[14] N.S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Drowsy Instruction Caches: Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-Bank Prediction," Proc. Int'l Symp. Microarchitecture (MICRO), pp. 219-230, 2002.
[15] S.-H. Yang, B. Falsafi, M.D. Powell, K. Roy, and T.N. Vijaykumar, "An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA), pp. 147-158, 2001.
[16] J.S. Hu, A. Nadgir, N. Vijaykrishnan, M.J. Irwin, and M. Kandemir, "Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management," Proc. Int'l Symp. Low Power Electronics Design (ISLPED), pp. 402-407, 2003.
[17] Y. Meng, T. Sherwood, and R. Kastner, "On the Limits of Leakage Power Reduction in Caches," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA), pp. 154-165, 2004.
[18] S. Petit, J. Sahuquillo, J.M. Such, and D. Kaeli, "Exploiting Temporal Locality in Drowsy Cache Policies," Proc. Conf. Computing Frontiers (CF), pp. 371-377, 2005.
[19] D. Nicolaescu, B. Salamat, A. Veidenbaum, and M. Valero, "Fast Speculative Address Generation and Way Caching for Reducing l1 Data Cache Energy," Proc. Int'l Conf. Computer Design (ICCD), pp. 101-107, 2006.
[20] H. Aydin, R. Melhem, D. Mossé, and P.M. Alvarez, "Dynamic and Aggressive Scheduling Techniques for Power-aware Real-Time Systems," Proc. IEEE Real-Time Systems Symp. (RTSS), pp. 95-105, 2001.
[21] C.M. Krishna and Y.-H. Lee, "Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems," IEEE Trans. Computers, vol. 52, no. 12, pp. 1586-1593, Dec. 2003.
[22] G. Quan and X. Hu, "Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processors," Proc. Conf. Design Automation and Test in Europe (DATE), pp. 782-787, 2002.
[23] Y. Shin, K. Choi, and T. Sakurai, "Power Optimization of Real-Time Embedded Systems on Variable Speed Processors," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 365-368, 2000.
[24] F. Yao, A. Demers, and S. Shenker, "A Scheduling Model for Reduced CPU Energy," Proc. IEEE Symp. Foundations of Computer Science (FOCS), pp. 374-382, 1995.
[25] I. Hong, M. Potkonjak, and M.B. Srivastava, "On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage Processor," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 653-656, 1998.
[26] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M.B. Srivastava, "Power Optimization of Variable Voltage Core-Based Systems," Proc. Design Automation Conf. (DAC), pp. 176-181, 1998.
[27] Y.-H. Lee, K.P. Reddy, and C.M. Krishna, "Scheduling Techniques for Reducing Leakage Power in Hard Real-Time Systems," Proc. Euromicro Conf. Real-Time Systems (ECRTS), pp. 105-112, 2003.
[28] L. Niu and G. Quan, "Reducing Both Dynamic and Leakage Energy Consumption for Hard Real-Time Systems," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 140-148, 2004.
[29] L. Yan, J. Luo, and N.K. Jha, "Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-Time Embedded Systems," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 30-38, 2003.
[30] C.H. Kim and K. Roy, "Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED), pp. 251-254, 2002.
[31] N. Azizi, A. Moshovos, and F.N. Najm, "Low-Leakage Asymmetric-Cell SRAM," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 701-715, Nov. 2003.
[32] L. Li, I. Kadayif, Y.-F. Tsai, N. Vijaykrishnan, M. Kandemir, M.J. Irwina, and A. Sivasubramaniam, "Leakage Energy Management in Cache Hierarchies," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 131-140, 2002.
[33] S. Velusamy, K. Sankaranarayanan, and D. Parikh, "Adaptive Cache Decay Using Formal Feedback Control," Proc. Workshop Memory Performance Issues, pp. 1-10, 2002.
[34] W. Zhang, J.S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, "Compiler-Directed Instruction Cache Leakage Optimization," Proc. Int'l Symp. Microarchitecture (MICRO), pp. 208-218, 2002.
[35] W. Zhang, M. Karakoy, M. Kandemir, and G. Chen, "A Compiler Approach for Reducing Data Cache Energy," Proc. Int'l Conf. Supercomputing (ICS), pp. 76-85, 2003.
[36] G. Chen, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, and M. Wolczko, "Tracking Object Life Cycle for Leakage Energy Optimization," Proc. IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 213-218, 2003.
[37] J. Liu, Real-Time Systems. Prentice-Hall, 2000.
[38] I. Puaut and D. Decotigny, "Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems," Proc. IEEE Int'l Real-Time Systems Symp. (RTSS), pp. 114-123, 2002.
[39] ARM946E-S, semiconductor/ asic/ipcorelibrary/intellectureproperties/ processorcores/armcores ddi0201_a946es.pdf, 2011.
[40] W. Kim, J. Kim, and S. Min, "A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 788-794, 2002.
[41] Cortex-R4F,, 2009.
[42] Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, "Microarchitectural Techniques for Power Gating of Execution Units," Proc. Int'l Symp. Low-Power Electronics and Design (ISLPED), pp. 32-37, 2004.
[43] Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, "Hotleakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects," Technical Report CS-2003-05, Univ. of Virginia, Dept. of Computer Science, http://lava.cs. virginia.eduHotLeakage/, 2003.
[44] D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 83-94, 2000.
[45] Y. Li, D. Parikh, and Y. Zhang, "State-Preserving vs. Non-State-Preserving Leakage Control in Caches," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 22-27, 2004.
[46] "SNU Real-Time Benchmarks," index.html, 2009.
[47] X. Vera, B. Lisper, and J.L. Xue, "Data Cache Locking for Higher Program Predictability," Proc. ACM SIGMETRICS, pp. 272-282, 2003.
[48] M. Campoy, A.P. Ivars, and J.V.B. Mataix, "Static Use of Locking Caches in Multitask Preemptive Real-Time Systems," Proc. IEEE/IEE Real-Time Embedded Systems Workshop, pp. 1-6, 2001.
[49] D. Kirk and J.K. Strosnider, "SMART (Strategic Memory Allocation for Real-Time) Cache Design Using the MIPS R3000," Proc. 11th IEEE Real-Time Systems Symp. (RTSS), pp. 322-330, 1990.
[50] B.D. Bui, M. Caccamo, L. Sha, and J. Martinez, "Impact of Cache Partitioning on Multi-Tasking Real Time Embedded Systems," Proc. 14th IEEE Int'l Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 101-110, 2008.
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