The Community for Technology Leaders
RSS Icon
Issue No.06 - June (2011 vol.60)
pp: 753-766
Mong-Ling Chiao , Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Da-Wei Chang , Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
A Flash Translation Layer (FTL) provides a block device interface on top of flash memory to support disk-based file systems. Due to the erase-before-write feature of flash memory, an FTL usually performs out-of-place updates and uses a cleaning procedure to reclaim stale data. A hybrid address translation (HAT)-based FTL combines coarse-grained and fine-grained address translation to achieve good performance while keeping the size of the mapping information small. In this paper, we propose a new HAT-based FTL, called ROSE, which includes three novel techniques for reducing the cleaning cost. First, it reduces high-cost reclamation by preventing data in an entire-block sequential write from being placed into multiple physical blocks while eliminating the cleaning cost resulting from mispredicting random or semisequential writes as sequential ones. Second, it uses a merge-aware cleaning policy that considers both the block age and the merge cost in a HAT-based FTL for improving the cleaning efficiency. Third, it delays the erasure of obsolete blocks and reuses their free pages for buffering more writes. Simulation results show that the proposed FTL outperforms existing HAT-based FTLs in terms of both cleaning cost and flash write time by up to 47 times and 1.6 times, respectively.
storage management, flash memories, merge-aware cleaning policy, flash translation layer, NAND flash memory, hybrid address translation, disk-based file systems, erase-before-write feature, coarse-grained address translation, fine-grained address translation, ROSE FTL, Cleaning, Flash memory, Switches, Memory management, Writing, File systems, Merging, flash translation layer (FTL)., Storage management, performance, NAND flash memory
Mong-Ling Chiao, Da-Wei Chang, "ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation", IEEE Transactions on Computers, vol.60, no. 6, pp. 753-766, June 2011, doi:10.1109/TC.2011.67
[1] J. Kim, J.M. Kim, S.H. Noh, S.L. Min, and Y. Cho, "A Space-Efficient Flash Translation Layer for Compact-Flash Systems," IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[2] C.H. Wu, H.H. Lin, and T.W. Guo, "An Adaptive Flash Translation Layer for High-Performance Storage Systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 953-965, June 2010.
[3] S.W. Lee, D.J. Park, T.S. Chung, D.H. Lee, S. Park, and H.J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Trans. Embedded Computing Systems, vol. 6, no. 3, July 2007.
[4] J.U. Kang, H. Jo, J.S. Kim, and J. Lee, "A Superblock-Based Flash Translation Layer for NAND Flash Memory," Proc. Sixth ACM and IEEE Int'l Conf. Embedded Software, pp. 161-170, 2006.
[5] S. Lee, D. Shin, Y.J. Kim, and J. Kim, "LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems," ACM SIGOPS Operating Systems Rev., vol. 42, no. 6, pp. 36-42, Oct. 2008.
[6] C. Park, W. Cheon, Y. Lee, M.S. Jung, W. Cho, and H. Yoon, "A Re-Configurable FTL (Flash Translation Layer) Architecture for NAND Flash Based Applications," ACM Trans. Embedded Computing Systems, vol. 7, no. 4, July 2008.
[7] Intel Corporation, "Understanding the Flash Translation Layer (FTL) Specification," Application Note AP-684, Dec. 1998.
[8] Intel Corporation, "Software Concerns of Implementing a Resident Flash Disk."
[9] Intel Corporation "FTL Logger Exchanging Data with FTL Systems."
[10] A. Ban, "Flash File System," US Patent No. 5,404,485, 1995.
[11] A. Ban and R. Hasharon, "Flash File System Optimized for Page-Mode Flash Technologies," US Patent No. 5,937,425, 1999.
[12] Toshiba "1G × 8 Bit NAND Flash Memory (TC58NVG3D1DT G00)," Datasheet, 2007.
[13] D. Kang, D. Jung, J.-U. Kang, and J.-S. Kim, "μ-Tree: An Ordered Index Structure for NAND Flash Memory," Proc. Seventh ACM and IEEE Int'l Conf. Embedded Software (EMSOFT '07), pp.144-153, Oct. 2007.
[14] Y.G. Lee, D. Jung, D. Kang, and J.S. Kim, "μ-FTL: A Memory Efficient Flash Translation Layer Supporting Multiple Mapping Granularities," Proc. Eighth ACM and IEEE Int'l Conf. Embedded Software (EMSOFT '08), pp. 21-30, Oct. 2008.
[15] P. Torelli, "The Microsoft Flash File System," Dr. Dobb's J., pp. 62-72, Feb. 1995.
[16] A. Kawaguchi, S. Nishioka, and H. Motoda, "A Flash-Memory Based File System," Proc. USENIX 1995 Winter Technical Conf., pp. 155-164, Jan. 1995.
[17] M.L. Chiang and R.C. Chang, "Cleaning Policies in Mobile Computers Using Flash Memory," J. Systems and Software, vol. 48, no. 3, pp. 213-231, 1999.
[18] H.J. Kim and S.G. Lee, "An Effective Flash Memory Manager for Reliable Flash Memory Space Management," IEICE Trans. Information and Systems, vol. E85-D, no. 6, pp. 950-964, 2002.
[19] H. Kim and S. Ahn, "BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage," Proc. Sixth USENIX Conf. File and Storage Technologies, pp. 239-252, 2008.
[20] M. Wu and W. Zwaenepoel, "eNVy: A Non-Volatile, Main Memory Storage System," Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '94), pp. 86-97, Dec. 1994.
[21] T13 Technical Committee, ATA/ATAPI Command Set-2, 2010.
[22] Samsung Electronics, "512M x 8 Bit/256M x 16 Bit NAND Flash Memory," Datasheet, datasheets/ 700389215_DS.pdf, 2005.
[23] J. Katcher, "PostMark: A New File System Benchmark," x86_64postmark- 1.51-19.42.x86_64.html , 2009.
[24] K. Bates and B. McNutt OLTP I/O Traces, http://traces.cs.umass. edu/index.php/storage storage, 2007.
[25] Filebench File System Benchmark, filebench, 2009.
23 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool