Issue No. 04 - April (2011 vol. 60)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.123
Preeti Ranjan Panda , Indian Institute of Technology Delhi, New Delhi
M. Balakrishnan , Indian Institute of Technology Delhi, New Delhi
Anant Vishnoi , Indian Institute of Technology Delhi, New Delhi
During postsilicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyser. In order to reduce the transfer time and save expensive logic analyser memory, we propose to compress the cache contents on their way out. We present a hardware compression engine for cache data using a Cache-Aware Compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression. Experimental results indicate that the technique results in 7-31 percent better compression than one that treats the data as just one long bit stream. We also describe and evaluate a parallel compression architecture that uses multiple compression engines, resulting in a 54 percent reduction in transfer time.
Postsilicon validation, processor debug, cache compression.
Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi, "Compressing Cache State for Postsilicon Processor Debug", IEEE Transactions on Computers, vol. 60, no. , pp. 484-497, April 2011, doi:10.1109/TC.2010.123