Pages: pp. 450-451
IT is with great pleasure that we introduce this special section on Chips and Architectures for Emerging Technologies and Applications to the audience of the IEEE Transactions on Computers.
We are currently witnessing a technology advancement which is making the gap between the present and future much narrower than it has ever been. The purpose of this special section is to showcase highly innovative, creative, and futuristic chip architectures and functionalities that can range from new paradigms in reconfigurable systems architectures, to adaptive, organic, ubiquitous, and biologically inspired computing, to new classes of chip implants, or any other highly innovative human-to-computer interface.
This special section includes two papers, which we hope will offer an interesting perspective on the challenges involved in designing integrated circuits and architectures that leverage the capabilities of emerging technologies in novel applications.
The first paper, ``Exploring the Potential of Threshold Logic for Cryptography-Related Operations,'' by Alessandro Cilardo, investigates the application of a non-Boolean computational paradigm to cryptographic applications. More specifically, the author demonstrates the power of linear Threshold Logic functions, which are enabled by new technologies such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), towards performing fundamental cryptographic operations. An architecture for implementing such operations, namely a Montgomery modular reduction and multiplication, is also introduced and its intrinsic superiority to traditional Boolean computational models in demonstrated.
The second paper, ``3D Integration of CMOL Structures for FPGA Applications,'' by Z. Abid, Ming Liu, and Wei Wang, introduces a combination of hybrid CMOS/nanoelectronic (CMOL) circuits and 3D integration, in order to develop a 3D CMOL technology with particular emphasis on designing Field-Programmable Gate-Array (FPGA) chips. The authors discuss the architecture, 3D integration, defect tolerance and performance aspects of this technology, as well as its breakthrough potential for developing the next generation of FPGAs.
We would like to thank the previous editor-in-chief of the IEEE Transactions on Computers, Dr. Fabrizio Lombardi, for suggesting that we organize this special section, the current editor-in-chief Dr. Albert Y. Zomaya, for hosting this section, and all of the editorial staff for the support in the making of the issue. Additionally, we would like to thank the authors of the submitted papers and the numerous reviewers whose contributions made this special section possible.