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Issue No. 02 - February (2011 vol. 60)
ISSN: 0018-9340
pp: 266-281
Jean-Luc Beuchat , University of Tsukuba, Tsukuba
Jérémie Detrey , INRIA Nancy - Grand Est, Nancy
Nicolas Estibals , INRIA Nancy - Grand Est, Nancy
Eiji Okamoto , University of Tsukuba, Tsukuba
Francisco Rodríguez-Henríquez , Av. Instituto Politenico Nacional No. 2508, México City
This paper is devoted to the design of fast parallel accelerators for the cryptographic \eta_T pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies that we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the \eta_T pairing over {\bf F}_{2^m} and {\bf F}_{3^m}. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the \eta_T pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area–time trade-off compared to previously published coprocessors.
Tate pairing, \eta_T pairing, elliptic curve, finite field arithmetic, Karatsuba multiplier, hardware accelerator, FPGA.

E. Okamoto, F. Rodríguez-Henríquez, N. Estibals, J. Detrey and J. Beuchat, "Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves," in IEEE Transactions on Computers, vol. 60, no. , pp. 266-281, 2010.
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