Issue No. 01 - January (2011 vol. 60)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.202
Weikang Qian , University of Minnesota, Minneapolis
Xin Li , University of Minnesota, Minneapolis
Marc D. Riedel , University of Minnesota, Minneapolis
Kia Bazargan , University of Minnesota, Minneapolis
David J. Lilja , University of Minnesota, Minneapolis
Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors.
Stochastic logic, reconfigurable hardware, fault-tolerant computation.
K. Bazargan, M. D. Riedel, W. Qian, X. Li and D. J. Lilja, "An Architecture for Fault-Tolerant Computation with Stochastic Logic," in IEEE Transactions on Computers, vol. 60, no. , pp. 93-105, 2010.