Issue No. 01 - January (2011 vol. 60)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.204
Shantanu Gupta , University of Michigan, Ann Arbor
Shuguang Feng , University of Michigan, Ann Arbor
Amin Ansari , University of Michigan, Ann Arbor
Scott Mahlke , University of Michigan, Ann Arbor
Aggressive technology scaling to 45 nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-chip caches, it is important to protect these SRAM structures against lifetime and manufacture-time failures. Designers typically overprovision caches with additional resources to overcome hard faults. However, static allocation and binding of redundant spares results in low utilization of the extra resources and ultimately limits the number of defects that can be tolerated. This work re-examines the design of process-variation-tolerant on-chip caches with a focus on providing the flexibility and dynamic reconfigurability necessary to tolerate large numbers of defects with modest hardware overhead. Our approach, ZerehCache, virtually reorganizes the cache data array using a permutation network to provide more degrees of freedom for spare allocation. A graph coloring algorithm is used to configure the network and identify the proper mapping of replacement elements. We perform an extensive design space exploration of both L1/L2 caches to identify several Pareto-optimal ZerehCaches. Given these optimal design points, we employ ZerehCache to extend the effective lifetime of the on-chip caches and prevent early lifetime failures. Finally, yield analysis studies performed on a population of 1,000 chips at the 45 nm technology node demonstrated that an L1 design with 16 percent overhead and an L2 design with eight percent area overhead achieve yields of 99 percent and 96 percent, respectively.
Process variation, wearout, fault-tolerant cache memories, manufacturing yield.
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott Mahlke, "Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines", IEEE Transactions on Computers, vol. 60, no. , pp. 35-49, January 2011, doi:10.1109/TC.2010.204