Issue No. 11 - November (2010 vol. 59)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.58
Alexandre (Alex) Yakovlev , Newcastle University, Newcastle Upon Tyne
Andrey Mokhov , Newcastle University, Newcastle upon Tyne
The paper introduces a new formal model for specification and synthesis of control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG), captures concurrency and choice in a system's behavior in a compact and efficient way. It has advantages over widely used interpreted Petri Nets and Finite State Machines for a class of systems which have many behavioral scenarios defined on the same set of actions, e.g., CPU microcontrollers. The CPOG model has potential applications in the area of microcontrol synthesis and brings new methods for modeling concurrency into the application domain of modern and future processor architectures. The paper gives the formal definition of the CPOG model, formulates and solves the problem of CPOG synthesis, and introduces various optimization techniques. The presented ideas can be applied for CPU control synthesis as well as for synthesis of different kinds of event-coordination circuits often used in data coding and communication in digital systems, as demonstrated with several application examples.
Logic synthesis, concurrency, partial orders, asynchronous circuits, microarchitecture.
Alexandre (Alex) Yakovlev, Andrey Mokhov, "Conditional Partial Order Graphs: Model, Synthesis, and Application", IEEE Transactions on Computers, vol. 59, no. , pp. 1480-1493, November 2010, doi:10.1109/TC.2010.58