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Issue No.10 - October (2010 vol.59)

pp: 1378-1391

Hagit Attiya , Technion, Israel

David Hay , Columbia University, New York

Isaac Keslassy , Technion, Israel

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.186

ABSTRACT

Most common network protocols transmit variable size packets, whereas contemporary switches still operate with fixed- size cells, which are easier to transmit and buffer. This necessitates packet segmentation and reassembly modules, resulting in significant computation and communication overhead that might be too costly as switches become faster and bigger. It is, therefore, imperative to investigate an alternative mode of scheduling in which packets are scheduled contiguously over the switch fabric. This paper investigates the cost of packet-mode scheduling for the combined input-output-queued (CIOQ) switch architecture. We devise frame-based schedulers that allow a packet-mode CIOQ switch with small speedup to mimic an ideal output-queued switch, with bounded relative queuing delay. The schedulers are pipelined and based on matrix decomposition. Our schedulers demonstrate a trade-off between the switch speedup and the relative queuing delay incurred while mimicking an output-queued switch. When the switch is allowed to incur high relative queuing delay, a speedup arbitrarily close to two suffices to mimic an ideal output-queued switch. This implies that packet-mode scheduling does not require higher speedup than a cell-based scheduler. The relative queuing delay can be significantly reduced with just a doubling of the speedup. We further show that it is impossible to achieve zero relative queuing delay (that is, a perfect emulation), regardless of the switch speedup. In addition, simpler algorithms can mimic an output-queued switch with a bounded buffer size, using speedup arbitrarily close to one. Simulations confirm that packet-mode emulation with reasonable relative queuing delay can be achieved with moderate speedup. Furthermore, a simple and practical heuristic is shown by simulations to also provide effective packet-mode emulation.

INDEX TERMS

Internetworking, packet-switching networks, routers, sequencing and scheduling.

CITATION

Hagit Attiya, David Hay, Isaac Keslassy, "Packet-Mode Emulation of Output-Queued Switches",

*IEEE Transactions on Computers*, vol.59, no. 10, pp. 1378-1391, October 2010, doi:10.1109/TC.2009.186REFERENCES

- [1]
WAN Packet Size Distribution, the Nat'l Laboratory for Applied Network Research. - [2]
Cisco 12000 Series Gigabit Switch Routers, Cisco Systems, Inc., 2009.- [3] P. Giaccone, E. Leonardi, B. Prabhakar, and D. Shah, "Delay Bounds for Combined Input-Output Switches with Low Speedup,"
Performance Evaluation, vol. 55, nos. 1/2, pp. 113-128, Jan. 2004.- [4] A. Charny, P. Krishna, N. Patel, and R. Simcoe, "Algorithms for Providing Bandwidth and Delay Guarantees in Input-Buffered Crossbars with Speedup,"
Proc. IEEE/IFIP Int'l Workshop Quality of Service (IWQoS), pp. 235-244, 1998.- [5] S.T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, "Matching Output Queueing with a Combined Input Output Queued Switch,"
Proc. IEEE INFOCOM, pp. 1169-1178, 1999.- [6] P. Krishna, N. Patel, A. Charny, and R. Simcoe, "On the Speedup Required for Work-Conserving Crossbar Switches,"
IEEE J. Selected Areas Comm., vol. 17, no. 6, pp. 1057-1066, June 1999.- [7] B. Prabhakar and N. McKeown, "On the Speedup Required for Combined Input and Output Queued Switching,"
Automatica, vol. 35, no. 12, pp. 1909-1920, Dec. 1999.- [8] D. Stephens and H. Zhang, "Implementing Distributed Packet Fair Queueing in a Scalable Architecture,"
Proc. IEEE INFOCOM, pp. 282-290, 1998.- [9] I. Stoica and H. Zhang, "Exact Emulation of an Output Queueing Switch by a Combined Input Output Queueing Switch,"
Proc. IEEE/IFIP Int'l Workshop Quality of Service (IWQoS), pp. 218-224, 1998.- [10] K. Kar, T.V. Lakshman, D. Stiliadis, and L. Tassiulas, "Reduced Complexity Input Buffered Switches,"
Proc. Conf. HOT Interconnects, pp. 13-20, 2000.- [11]
ERX-700/1400, Edge Routing Switch, Unisphere Solutions, Inc., 2000.- [12] M. Ajmone Marsan, A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, "Packet-Mode Scheduling in Input-Queued Cell-Based Switches,"
IEEE/ACM Trans. Networking, vol. 10, no. 5, pp. 666-678, Oct. 2002.- [13] Y. Ganjali, A. Keshavarzian, and D. Shah, "Input Queued Switches: Cell Switching vs. Packet Switching,"
Proc. IEEE INFOCOM, vol. 3, pp. 1651-1658, Mar. 2003.- [14] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, "Achieving 100 % Throughput in an Input-Queued Switch,"
IEEE Trans. Comm., vol. 47, no. 8, pp. 1260-1267, Aug. 1999.- [15] D. Guez, A. Kesselman, and A. Rosén, "Packet-Mode Policies for Input-Queued Switches,"
Proc. ACM Symp. Parallelism in Algorithms and Architectures (SPAA), pp. 93-102, 2004.- [16] J.S. Turner, "Strong Performance Guarantees for Asynchronous Buffered Crossbar Schedulers,"
IEEE/ACM Trans. Networking, vol. 17, no. 4, pp. 1017-1028, Aug. 2009.- [17] S.T. Chuang, S. Iyer, and N. McKeown, "Practical Algorithms for Performance Guarantees in Buffered Crossbars,"
Proc. IEEE INFOCOM, 2005.- [18] E. Altman, Z. Liu, and R. Righter, "Scheduling of an Input-Queued Switch to Achieve Maximal Throughput,"
Probability in the Eng. and Informational Sciences, vol. 14, pp. 327-334, 2000.- [19] C.-S. Chang, D. Lee, and Y. Jou, "Load Balanced Birkhoff-Von Neumann Switches, Part I: One-Stage Buffering,"
Computer Comm., vol. 25, pp. 611-622, 2002.- [20] A. Hung, G. Kesidis, and N. McKeown, "ATM Input-Buffered Switches with Guaranteed-Rate Property,"
Proc. IEEE Symp. Computers and Comm. (ISCC), pp. 331-335, 1998.- [21] I. Keslassy, M. Kodialam, T.V. Lakshman, and D. Stiliadis, "On Guaranteed Smooth Scheduling for Input-Queued Switches,"
IEEE/ACM Trans. Networking, vol. 13, no. 6, pp. 1364-1375, Dec. 2005.- [22] X. Li and M. Hamdi, "On Scheduling Optical Packet Switches with Reconfiguration Delay,"
IEEE J. Selected Areas Comm., vol. 21, no. 7, pp. 1156-1164, Sept. 2003.- [23] B. Towles and W. Dally, "Guaranteed Scheduling for Switches with Configuration Overhead,"
IEEE/ACM Trans. Networking, vol. 11, no. 5, pp. 835-847, Oct. 2003.- [24] T. Weller and B. Hajek, "Scheduling Nonuniform Traffic in a Packet-Switching System with Small Propagation Delay,"
IEEE/ACM Trans. Networking, vol. 5, no. 6, pp. 813-823, Dec. 1997.- [25] N. McKeown, "The iSLIP Scheduling Algorithm for Input-Queued Switches,"
IEEE/ACM Trans. Networking, vol. 7, no. 2, pp. 188-201, Apr. 1999.- [26] S. Iyer and N. McKeown, "Making Parallel Packet Switches Practical,"
Proc. IEEE INFOCOM, pp. 1680-1687, 2001.- [27] L. Kleinrock,
Queuing Systems, vol. II. John Wiley & Sons, 1975.- [28] G. Birkhoff, "Tres Observaciones Sobre El Algebra Lineal,"
Univ. Nac. Tucuman Rev. Ser. A, vol. 5, pp. 147-151, 1946.- [29] J. von Neumann, "A Certain Zero-Sum Two-Person Game Equivalent to the Optimal Assignment Problem,"
Contributions to the Theory of Games, vol. 2, pp. 5-12, 1953.- [30] L. Dulmage and I. Halperin, "On a Theorem of Frobenius-Konig and J. von Neumann's Game of Hide and Seek,"
Trans. Royal Soc. Canada III, vol. 49, pp. 23-29, 1955.- [31] Y. Li, S. Panwar, and H. Chao, "Exhaustive Service Matching Algorithms for Input Queued Switches,"
Proc. IEEE Workshop High Performance Switching Routing, pp. 253-258, 2004.- [32] Cooperative Assoc. for Internet Data Analysis (CAIDA), http:/www.caida.org/, 2009.
- [33] A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, "A Framework for Differential Frame-Based Matching Algorithms in Input-Queued Switches,"
Proc. IEEE INFOCOM, 2004.- [34] P. Pappu, J. Turner, and K. Wong, "Work-Conserving Distributed Schedulers for Terabit Routers,"
Proc. ACM SIGCOMM, pp. 257-268, 2004. |