The Community for Technology Leaders
Green Image
Issue No. 10 - October (2010 vol. 59)
ISSN: 0018-9340
pp: 1363-1377
Holger Lange , Technische Universität Darmstadt, Darmstadt
Andreas Koch , Technische Universität Darmstadt, Darmstadt
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23{\times} times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89 percent of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility/performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.
Reconfigurable computing, FPGA, hardware accelerator, memory system, operating system integration, virtual memory.

H. Lange and A. Koch, "Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization," in IEEE Transactions on Computers, vol. 59, no. , pp. 1363-1377, 2009.
92 ms
(Ver 3.3 (11022016))