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Issue No. 09 - September (2010 vol. 59)
ISSN: 0018-9340
pp: 1264-1280
Kris Gaj , George Mason University, Fairfax
Mohammed Khaleeluddin , Hughes Network Systems, Germantown
Marcin Rogawski , George Mason University, Fairfax
Ramakrishna Bachimanchi , Thomas Jefferson National Accelerator Facility
Paul Kohlbrenner , George Mason University, Fairfax
Soonhak Kwon , Sungkyunkwan University, Suwon
Patrick Baier , Siemens PLM Software
Hoang Le , University of Southern California, Los Angeles
A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proof-of-concept design by Pelzl et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the area-time product. The ECM architecture has been ported across five different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with the highly optimized software implementation, GMP-ECM, has been performed. Our results indicate that low-cost families of FPGAs, such as Spartan-3 and Spartan-3E, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio, without the use of embedded FPGA resources, such as embedded multipliers.
Cipher-breaking, factoring, ECM, FPGA, NFS.
Kris Gaj, Mohammed Khaleeluddin, Marcin Rogawski, Ramakrishna Bachimanchi, Paul Kohlbrenner, Soonhak Kwon, Patrick Baier, Hoang Le, "Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve", IEEE Transactions on Computers, vol. 59, no. , pp. 1264-1280, September 2010, doi:10.1109/TC.2009.191
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