Issue No. 09 - September (2010 vol. 59)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.109
Jack Whitham , University of York, York
Neil Audsley , University of York, York
Superscalar out-of-order CPU designs can achieve higher performance than simpler in-order designs through exploitation of instruction-level parallelism in software. However, these CPU designs are often considered to be unsuitable for hard real-time systems because of the difficulty of guaranteeing the worst-case execution time (WCET) of software. This paper proposes and evaluates modifications for a superscalar out-of-order CPU core to allow instruction-level parallelism to be exploited without sacrificing time predictability and support for WCET analysis. Experiments using the M5 O3 CPU simulator show that WCETs can be two-four times smaller than those obtained using an idealized in-order CPU design, as instruction-level parallelism is exploited without compromising timing safety.
Real-time and embedded systems, superscalar and dynamically scheduled microarchitectures.
J. Whitham and N. Audsley, "Time-Predictable Out-of-Order Execution for Hard Real-Time Systems," in IEEE Transactions on Computers, vol. 59, no. , pp. 1210-1223, 2010.