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Issue No. 09 - September (2010 vol. 59)
ISSN: 0018-9340
pp: 1187-1199
Igor Valerievich Zotov , Kursk Technical University, Kursk
ABSTRACT
The work presents a distributed hardware-level barrier mechanism for n-dimensional mesh-connected MIMD computers, called Distributed Virtual Bit-Slice Synchronizer (DVBSS). The proposed mechanism is structured around an m-bit dedicated control network, whose topology is a directed mesh-embeddable graph, with an additional m-bit-wide wraparound connection. By using a specific virtualization scheme making it possible to have p virtual m-bit barrier networks superposed on a physical one, the DVBSS model allows to synchronize more than m barrier groups. To minimize synchronization latency, the DVBSS scheme uses a distributed circulating wave clocking (DCW-clocking) technique to switch between virtual barrier networks in a pipeline fashion. The DVBSS scheme is shown to be general, configurable, and MPI-compatible. Unlike proposed distributed hardware barriers, and hardware tree-based schemes, the DVBSS mechanism accepts dynamically defined (possibly overlapping) barrier groups of arbitrary size and shape, allowing noncontiguous group member allocations.
INDEX TERMS
Barrier synchronization, dedicated barrier networks, hardware barriers, mesh-connected parallel computers.
CITATION
Igor Valerievich Zotov, "Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes", IEEE Transactions on Computers, vol. 59, no. , pp. 1187-1199, September 2010, doi:10.1109/TC.2010.15
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