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Issue No. 08 - August (2010 vol. 59)
ISSN: 0018-9340
pp: 1134-1137
Ron S. Waters , University of Texas at Austin, Austin, TX
Earl E. Swartzlander , University of Texas at Austin, Austin, TX
ABSTRACT
Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.
INDEX TERMS
High-speed multiplier, Wallace multiplier, Dadda multiplier.
CITATION
Ron S. Waters, Earl E. Swartzlander, "A Reduced Complexity Wallace Multiplier Reduction", IEEE Transactions on Computers, vol. 59, no. , pp. 1134-1137, August 2010, doi:10.1109/TC.2010.103
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