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Issue No.08 - August (2010 vol.59)
pp: 1105-1119
Suzana Stojković; , University of Niš, Serbia
Dragan Janković; , University of Niš, Serbia
Radomir S. Stanković; , University of Niš, Serbia
Decision diagrams (DDs) are a data structure that allows compact representation of discrete functions. The efficient construction of DDs in terms of space and time is often considered problem. A particular problem is that during the construction of a DD, a large number of temporary nodes are created. We address this problem in the case when the functions are specified in the PLA format. A common practice is to construct a DD by recursively processing all the cubes in PLA specification. The DD representing a subfunction defined by a single cube is merged with the DD for the subfunction defined by all the previously processed cubes. We proposed a method of reordering and partitioning the set of cubes in PLA specification that results in the reduction of both space and time complexities of the construction of DDs. First, we arrange cubes by their suffices. Then we partition the set of cubes, construct DDs for the subfunctions representing each partition separately, and merge them into a final DD. The reordering and partitioning ensures that these intermediary decision diagrams never exceed a certain size which is controlled by the size of the partitions. In this way, the number of operations on the nodes during the merging decision diagrams is reduced. This reduction results in a decrease both in the number of temporary nodes and construction time. The proposed method is used for the construction of DDs for the set of standard benchmark functions. The experiments show that the total number of created nodes is reduced on average by 34.65 percent, while the construction time is decreased by 48.6 percent.
Cubes, decision diagrams, decision diagrams construction.
Suzana Stojković;, Dragan Janković;, Radomir S. Stanković;, "An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set", IEEE Transactions on Computers, vol.59, no. 8, pp. 1105-1119, August 2010, doi:10.1109/TC.2010.21
[1] K.S. Brace, R.L. Rudell, and R.E. Bryant, "Efficient Implementation of a BDD Package," Proc. Design Automation Conf., pp. 40-45, 1990.
[2] R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.
[3] R. Drechsler and B. Becker, "Ordered Kronecker Functional Decision Diagrams—A Data Structure for Representation and Manipulation of Boolean Functions," IEEE Trans. CAD, vol. 17, no. 10, pp. 965-973, Oct. 1998.
[4] R. Drechsler and B. Becker, Binary Decision Diagrams: Theory and Implementation. Kluwer Academic Publishers, 1998.
[5] G.D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Kluwer Academic Publishers, 1996.
[6] D.M. Miller, "Spectral Transformation of Multiple-Valued Decision Diagrams," Proc. 24th Int'l Symp. Multiple-Valued Logic, pp. 89-96, 1994.
[7] D.M. Miller and R. Drechsler, "Implementing a Multiple-Valued Decision Diagram Package," Proc. 28th Int'l Symp. Multiple-Valued Logic, pp. 52-57, 1998.
[8] S. Minato, Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996.
[9] R.S. Stanković and J. Astola, Spectral Interpretation of Decision Diagrams. Springer-Verlag, 2003.
[10] S. Stojković, "UDDP—Universal Decision Diagram Package," Acta Electrica et Informatica, vol. 5, no. 1, pp. 34-41, 2005.
[11] D. Janković, "A New Approach in Implementation of MVL DD Package," Proc. Workshop Computational Intelligence, pp. 107-128, 2001.
[12] R. Drechsler, D. Janković, and R.S. Stanković, "Generic Implementation of Multi-Valued Logic Decision Diagram Packages," J. Multiple-Valued Logic and Soft Computing, vol. 11, pp. 1-18, 2005.
[13] R. Rudell, "Dynamic Variable Ordering for Ordered Binary Decision Diagrams," Proc. Int'l Conf. Computer-Aided Design, pp. 139-144, 1993.
[14] D. Janković, W. Guenther, and R. Drechsler, "Lower Bound Sifting for MDDs," Proc. 30th Int'l Symp. Multiple-Valued Logic, pp. 193-198, 2000.
[15] B. Yang, Y.-A. Chen, R.E. Bryant, and D.R. O'Hallaron, "Space- and Time-Efficient BDD Construction via Working Set Control," Proc. Asian-South Pacific Design Automation Conf., pp. 423-432, Feb. 1998.
[16] S. Minato, "Streaming BDD Manipulation," IEEE Trans. Computers, vol. 51, no. 5, pp. 474-485, May 2002.
[17] S. Minato and S. Ishihara, "Streaming BDD Manipulation for Large-Scale Combinatorial Problems," Proc. ACM/IEEE Design, Automation and Test in Europe (DATE '01), pp. 702-707, Mar. 2001.
[18] R. Ebnet, G. Fey, and R. Drechsler, Advanced BDD Optimization. Springer, 2005.
[19] H. Ochi, N. Ishiura, and S. Yajima, "Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing," Proc. Design Automation Conf., pp. 413-416, June 1991.
[20] H. Ochi, N. Ishiura, and S. Yajima, "Breadth-First Manipulation of Very Large Binary-Decision Diagrams," Proc. Int'l. Conf. Computer-Aided Design, pp. 413-416, Nov. 1993.
[21] R.K. Ranjan, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli, "High Performance BDD Package Based on Exploiting Memory Hierarchy," Proc. ACM/IEEE Design Automation Conf., pp. 635-640, June 1996.
[22] F. Somenzi, CUDD Release 2.4.1, CUDD/, 2010.
[23] Y.A. Chen, B. Yang, and R.E. Bryant, "Breadth-First with Depth-First BDD Construction: A Hybrid Approach," Technical Report CMU-CS-97-120, School of Computer Science, Carnegie Mellon Univ., 1997.
[24] B. Yang, Y.A. Chen, R.E. Brayant, and D.R. O'Hallaron, "Space- and Time-Efficient BDD Construction via Working Set Control," Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 423-432, 1998.
[25] I.K. Brayton, M. Chiodo, R. Hojati, T. Kam, K. Kodandapani, R.P. Kurshan, S. Maiik, A.L. Sangiovanni-Vincentelli, E.M. Sentovich, T. Shiple, K.J. Singh, and H.-Y. Wang, "BLIF-MV: An Interchange Format for Design Verification and Synthesis," Technical Report UCB/ERL M91/97, Electronics Research Lab, Univ. of California, Nov. 1991.
[26] R.K. Brayton, A.L. Sangiovanni-Vincentelli, C.T. McMullen, and G.D. Hactel, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
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