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Issue No. 07 - July (2010 vol. 59)
ISSN: 0018-9340
pp: 1000-1006
Haohuan Fu , Stanford University, Stanford
Oskar Mencer , Imperial College London, London
Wayne Luk , Imperial College London, London
ABSTRACT
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.
INDEX TERMS
Reconfigurable hardware, special-purpose and application-based systems, computer systems organization, computer arithmetic, general, numerical analysis, mathematics of computing.
CITATION

W. Luk, O. Mencer and H. Fu, "FPGA Designs with Optimized Logarithmic Arithmetic," in IEEE Transactions on Computers, vol. 59, no. , pp. 1000-1006, 2010.
doi:10.1109/TC.2010.51
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