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Issue No.07 - July (2010 vol.59)
pp: 922-932
Alodeep Sanyal , University of Massachusetts, Amherst
Ashesh Rastogi , Intel Corporation, Austin
Wei Chen , University of Massachusetts, Amherst
Sandip Kundu , University of Massachusetts, Amherst
With the scaling of CMOS technology, subthreshold, gate, and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together, they account for more than 25 percent of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called the loading effect. In this paper, we propose a pattern dependent steady-state leakage estimation technique that incorporates loading effect and accounts for all three major leakage components, namely the gate, band-to-band-tunneling, and subthreshold leakage and accounts for transistor stack effect. By observing a recursive relationship between gate leakage and loading effect, we further refine our leakage estimation technique by developing a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speedup of 18,000\rm X over SPICE simulation on smaller circuits, where SPICE simulation is feasible. Results also show that loading effect is a significant factor in leakage and worsens with technology scaling.
Subthreshold leakage, gate leakage, band-to-band-tunneling leakage, loading effect, Newton-Raphson method.
Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu, "An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects", IEEE Transactions on Computers, vol.59, no. 7, pp. 922-932, July 2010, doi:10.1109/TC.2010.75
[1] International Roadmap for Semiconductors, , 2008.
[2] P.E. Zeitzoff and J.E. Chung, "A Perspective from the 2003 ITRS: MOSFET Scaling Trends, Challenges, and Potential Solutions," IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 4-15, Jan./Feb. 2005.
[3] S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling," Proc. IEEE/ACM Design Automation Conf. (DAC '03), pp. 169-174, 2003.
[4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[5] S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits," Proc. Design and Test Europe Conf. (DATE '05), vol. 1, pp. 224-229, 2005.
[6] R. Rao, J. Burns, A. Devgan, and R. Brown, "Efficient Techniques for Gate Leakage Estimation," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '03), pp. 100-103, 2003.
[7] A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C.H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits," IEEE Micro, vol. 26, no. 2, pp. 68-80, Mar. 2006.
[8] H. Rahman and C. Chakrabarti, "A Leakage Estimation and Reduction Technique for Scaled CMOS Logic Circuits Considering Gate Leakage," Proc. Int'l Symp. Circuits and Systems, pp. 297-300, vol. 2, 2004.
[9] S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-Chip Sub-Threshold Leakage Power Prediction Model for Sub-0.18 μm CMOS," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '02), pp. 19-23, 2002.
[10] T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K.C. Saraswat, "High-Mobility Ultrathin Strained Ge MOSFETs on Bulk and SOI with Low Band-to-Band Tunneling Leakage: Experiments," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 990-999, May 2006.
[11] C. Hu et al., "BSIM4 Gate Leakage Model Including Source-Drain Partition," Proc. Int'l Electron Device Meeting, pp. 815-818, 2000.
[12] C. Hu et al., "BSIM4.5.0 Mosfet Model," User's Manual, 2004.
[13] K.N. Yang, H.T. Huang, M.J. Chen, Y.M. Lin, M.C. Yu, S.M. Jang, D.C.H. Yu, and M.S. Liang, "Characterization and Modeling of Edge Direct Tunneling (EDT) Leakage in Ultrathin Gate Oxide MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 6, pp. 1159-1164, June 2001.
[14] Y. Cao et al., "Spice Up Your MOSFET Modeling," IEEE Circuits and Devices Magazine, vol. 19, no. 4, pp. 17-23, July 2003.
[15] J.M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits. Prentice Hall, 2003.
[16] M. Drazdziulis and P. Larsson-Edefors, "A Gate Leakage Reduction Strategy for Future CMOS Circuits," Proc. European Solid-State Circuits Conf., pp. 317-320, 2003.
[17] D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Simultaneous Sub-Threshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design," Proc. Int'l Symp. Quality Electronic Design, pp. 287-292, 2003.
[18] D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits," IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 2, pp. 155-166, Feb. 2004.
[19] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical Analysis of Sub-Threshold Leakage Current for VLSI Circuits," IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 2, pp. 131-139, Feb. 2004.
[20] R. Bryant, "COSMOS: A Complied Simulator for MOS Circuits," Proc. IEEE/ACM Design Automation Conf. (DAC '87), pp. 9-16, 1987.
[21] E.M. Sentovich et al., SIS: Logic Synthesis of Synchronous and Asynchronous Sequential Circuit Program, Technical Report UCB/ERL M92/41, UC Berkeley, May 1992.
[22] NGSPICE: Mixed-Level/Mixed-Signal Circuit Simulator Based on Berkeley spice3f5, Cider1b1 and Xspice, Part of GPL'd Suite of Electronic Design Automation Tools (gEDA project).
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