The Community for Technology Leaders
RSS Icon
Issue No.07 - July (2010 vol.59)
pp: 905-921
Yoon Jae Seong , Seoul National University, Seoul, Korea
Eyee Hyun Nam , Seoul National University, Seoul, Korea
Jin Hyuk Yoon , Seoul National University, Seoul, Korea
Hongseok Kim , Seoul National University, Seoul, Korea
Jin-Yong Choi , Seoul National University, Seoul, Korea
Sookwan Lee , Seoul National University, Seoul, Korea
Young Hyun Bae , Seoul National University, Seoul, Korea
Jaejin Lee , Seoul National University, Seoul, Korea
Yookun Cho , Seoul National University, Seoul, Korea
Sang Lyul Min , Seoul National University, Seoul, Korea
Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.
Flash memory, flash translation layer (FTL), solid-state disk (SSD), storage system.
Yoon Jae Seong, Eyee Hyun Nam, Jin Hyuk Yoon, Hongseok Kim, Jin-Yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, Sang Lyul Min, "Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture", IEEE Transactions on Computers, vol.59, no. 7, pp. 905-921, July 2010, doi:10.1109/TC.2010.63
[1] N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M. Manasse, and R. Panigrahy, "Design Tradeoffs for SSD Performance," Proc. USENIX 2008 Technical Conf., 2008.
[2] A. Ban, Flash File System Optimized for Page-Mode Flash Technologies, US Patent no. 5,937,425, Aug. 1999.
[3] A. Ben-Aroya and S. Toledo, "Competitive Analysis of Flash-Memory Algorithms," Proc. 14th Ann. European Symp. Algorithms, pp. 100-111, Sept. 2006.
[4] A. Birrell, M. Isard, C. Thacker, and T. Wobber, "A Design for High-Performance Flash Disks," SIGOPS Operating Systems Rev., vol. 41, no. 2, Apr. 2007.
[5] Blktrace Manual Page, en/man8blktrace.html/, 2010.
[6] Btrecord Manual Page, manpages/ intrepid/en/man8btrecord.html/, 2010.
[7] Btreplay Manual Page, manpages/ intrepid/en/man8btreplay.html/, 2010.
[8] M.-L. Chiang, P.C.H. Lee, and R.-C. Chang, "Using Data Clustering to Improve Cleaning Performance for Flash Memory," Software: Practice and Experience, vol. 29, no. 3, pp. 267-290, Mar. 1999.
[9] Futuremark Corporation, "PCMark05 Whitepaper," http:/, 2010.
[10] E. Gal and S. Toledo, "Algorithms and Data Structures for Flash Memories," ACM Computing Surveys, vol. 37, no. 2, pp. 138-163, June 2005.
[11] C. Hwang, "Nanotechnology Enables a New Memory Growth Model," Proc. IEEE, vol. 91, no. 11, pp. 1765-1771, Nov. 2003.
[12] INCITS, "AT Attachment with Packet Interface—7, Volume 2— Parallel Transport Protocols and Physical Interconnect (ATA/ATAPI-7 V2)," Working Draft, Apr. 2004.
[13] INCITS, "AT Attachment with Packet Interface—7, Volume 3— Serial Transport Protocols and Physical Interconnect (ATA/ATAPI-7 V3)," Working Draft, Apr. 2004.
[14] IOmeter Project, http:/, 2010.
[15] M. Jackson, SAS Storage Architecture. MindShare Press, 2005.
[16] J.-U. Kang, H. Jo, J.-S. Kim, and J. Lee, "A Superblock-Based Flash Translation Layer for NAND Flash Memory," Proc. Sixth ACM Conf. Embedded Systems Software (EMSOFT '06), pp. 161-170, 2006.
[17] A. Kawaguchi, S. Nishioka, and H. Motoda, "A Flash-Memory Based File System," Proc. USENIX 1995 Winter Technical Conf., pp. 155-164, 1995.
[18] T. Kgil and T. Mudge, "FlashCache: A NAND Flash Memory File Cache for Low Power Web Servers," Proc. 2006 Int'l Conf. Compilers, Architecture and Synthesis for Embedded Systems (CASES '06), Oct. 2006.
[19] T. Kgil, D. Roberts, and T. Mudge, "Improving NAND Flash Based Disk Caches," Proc. 35th Int'l Symp. Computer Architecture (ISCA '08), pp. 327-338, June 2008.
[20] H. Kim and S. Ahn, "BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage," Proc. Sixth USENIX Conf. File and Storage Technologies (FAST '08), 2008.
[21] J. Kim, J.M. Kim, S.H. Noh, S.L. Min, and Y. Cho, "A Space-Efficient Flash Translation Layer for CompactFlash Systems," IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[22] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully Associative Sector Translation," ACM Trans. Embedded Computing Systems, vol. 6, no. 3, Jul. 2007.
[23] E.H. Nam, K.S. Choi, J. Choi, H.J. Min, and S.L. Min, "Hardware Platforms for Flash Memory/NVRAM Software Development," J. Computing Science and Eng., vol. 3, no. 3,pp. 181-194, Sept. 2009.
[24] R. Panabaker, "Hybrid Hard Disk & ReadyDrive Technology: Improving Performance and Power for Windows Vista Mobile PCs," , 2010.
[25] D.A. Patterson, G. Gibson, and R.H. Katz, "A Case for Redundant Arrays of Inexpensive Disks (RAID)," Proc. 1988 ACM SIGMOD, pp. 109-116, 1988.
[26] V. Prabhakaran, T.L. Rodeheffer, and L. Zhou, "Transactional Flash," Proc. Eighth USENIX Symp. Operating Systems Design and Implementation (OSDI '08), 2008.
[27] M. Rosenblum and J. Ousterhout, "The Design and Implementation of a Log-Structured File System," ACM Trans. Computer Systems, vol. 10, no. 1, pp. 26-52, Feb. 1992.
[28] C. Ruemmler and J. Wilkes, "An Introduction to Disk Drive Modeling," Computer, vol. 27, no. 3, pp. 17-28, Mar. 1994.
[29] Samsung Electronics, NAND Flash Memory Data Sheets, http:/, 2010.
[30] A. Sheikholeslami and P.G. Gulak, "A Survey of Circuit Innovations in Ferroelectric Random-Access Memories," Proc. IEEE, vol. 88, no. 5, pp. 667-689, May 2000.
[31] Transaction Processing Performance Council (TPC), TPC Benchmark C, http:/, 2010.
[32] C.-H. Wu and T.-W. Kuo, "An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '06), pp. 601-606. 2006.
[33] M. Wu and W. Zwaenepoel, "eNVy: A Non-Volatile, Main Memory Storage System," Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-6), pp. 86-97, 1994.
[34] J.H. Yoon, E.H. Nam, Y.J. Seong, H. Kim, B.S. Kim, S.L. Min, and Y. Cho, "Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture," IEEE Computer Architecture Letters, vol. 7, no. 1, pp. 17-20, Jan. 2008.
13 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool