The Community for Technology Leaders
RSS Icon
Issue No.07 - July (2010 vol.59)
pp: 891-904
Mirko Loghi , Politecnico di Torino, Torino
Olga Golubeva , Politecnico di Torino, Torino
Enrico Macii , Politecnico di Torino, Torino
Massimo Poncino , Politecnico di Torino, Torino
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be even pushed further by properly matching the partition to the memory access patterns. When leakage energy comes into play, however, idle memory blocks must be put into a proper low-leakage sleep state to actually save energy when not accessed. In this case, the matching becomes an instance of the power management problem, because moving to and from this sleep state requires additional energy. In this work, we propose an effective solution to the problem of the leakage-aware partitioning of a memory into disjoint subblocks; in particular, we target scratchpad memories, which are commonly used in some embedded systems as a replacement for caches. We show that, although the solution space is extremely large (for a N--block partition, all the combinations of N-1 address boundaries) and nonconvex, it is possible to prove a nontrivial property that considerably reduces the number of partition boundaries to be enumerated, therefore, making exhaustive exploration feasible. We are thus able to provide an optimal solution to the leakage-aware partitioning problem. Experiments on a different sets of embedded applications have shown that total energy savings larger than 60 percent on average can be obtained, with a marginal overhead in execution time, thanks to an effective implementation of the low-leakage sleep state.
Power optimization, leakage power, embedded design, memory hierarchy, scratchpad memory, partitioning algorithm.
Mirko Loghi, Olga Golubeva, Enrico Macii, Massimo Poncino, "Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking", IEEE Transactions on Computers, vol.59, no. 7, pp. 891-904, July 2010, doi:10.1109/TC.2010.43
[1] P. Panda and N. Dutt, Memory Issues in Embedded Systems-On-Chip: Optimization and Exploration. Kluwer Academic Publishers, 1999.
[2] A. Macii, L. Benini, and M. Poncino, Memory Design Techniques for Low-Energy Embedded Systems. Kluwer Academic Publishers, 2002.
[3] International Technology Roadmap for Semiconductors 2002 Edition, Semiconductor Industry Assoc., http:/, 2010.
[4] E. Macii, R. Mehra, and M. Poncino, "Micro-Architectural Power Estimation and Optimization," Handbook of EDA for IC Design, G. Martin, L. Lavagno, and L. Scheffer, eds., CRC Press, 2006.
[5] C. Su and A. Despain, "Cache Design Tradeoffs for Power and Performance Optimization: A Case Study," Proc. Int'l Symp. Low Power Design (ISLPD '95), pp. 63-68, Apr. 1995.
[6] W. Shiue and C. Chakrabarti, "Memory Exploration for Low-Power, Embedded Systems," Proc. 36th Ann. Conf. Design Automation (DAC '99), pp. 140-145, June 1999.
[7] S. Coumeri and D.E. Thomas, "Memory Modeling for System Synthesis," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 327-334, June 2000.
[8] L. Benini, L. Macchiarulo, A. Macii, E. Macii, and M. Poncino, "Layout-Driven Memory Synthesis for Embedded Systems-on-Chip," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 10, no. 2, pp. 96-105, Apr. 2002.
[9] F. Angiolini, L. Benini, and A. Caprara, "An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 11, pp. 1660-1676, Nov. 2005.
[10] O. Ozturk and M. Kandemir, "Nonuniform Banking for Reducing Memory Energy Consumption," Proc. Conf. Design, Automation and Test in Europe (DATE '05), pp. 814-819, Mar. 2005.
[11] S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," Proc. Int'l Symp. Computer Architecture (ISCA '01), pp. 240-251, June 2001.
[12] K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," Proc. Int'l Symp. Computer Architecture (ISCA '02), pp. 148-157, May 2002.
[13] M. Powell, S.H. Yang, B. Falsafi, K. Roy, and T.N. Vijaykumar, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '00), pp. 90-95, July 2000.
[14] M. Kandemir, M.J. Irwin, G. Chen, and I. Kolcu, "Compiler-Guided Leakage Optimization for Banked Scratch-Pad Memories," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 10, pp. 1136-1146, Oct. 2005.
[15] X. Lu and Y. Fu, "Reducing Leakage Power in Instruction Cache Using WDC for Embedded Processors," Proc. Asia South Pacific Design Automation Conf. (ASPDAC '05), pp. 1292-1295, Jan. 2005.
[16] O. Golubeva, M. Loghi, E. Macii, and M. Poncino, "Architectural Leakage-Aware Management of Partitioned Scratchpad Memories," Proc. Conf. Design, Automation and Test in Europe (DATE' 07), pp. 1665-1670, Apr. 2007.
[17] T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, Introduction to Algorithms, second ed., MIT Press/McGraw-Hill, 2001.
[18] J. Scott, L. Lee, J. Arends, and B. Moyer, "Designing the Low-Power M$\cdot$ CORE Architecture," Proc. IEEE Int'l. Symp. Computer Architecture Power Driven Microarchitecture Workshop, pp. 145-150, July 1998.
[19] T. Givargis and F. Vahid, "Platune: A Tuning Framework for System-on-a-Chip Platforms," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 11, pp. 1317-1327, Nov. 2002.
[20] M.R. Guthaus et al., "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," IEEE Fourth Ann. Workshop Workload Characterization, pp. 3-14, Dec. 2001.
[21] Simplescalar Toolset, http:/, 2010.
[22] M. Avriel, Nonlinear Programming: Analysis and Methods. Dover Publishing, 2003.
18 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool