Issue No. 04 - April (2010 vol. 59)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.187
Hao Zheng , University of South Florida, Tampa
Haiqiong Yao , University of South Florida, Tampa
Tomohiro Yoneda , National Institute of Informatics, Japan
Divide-and-conquer is essential to address state explosion in model checking. Verifying each individual component in a system, in isolation, efficiently requires an appropriate context, which traditionally is obtained by hand. This paper presents an efficient modular model checking approach for asynchronous design verification. It is equipped with a novel abstraction refinement method that can refine a component abstraction to be accurate enough for successful verification. It is fully automated, and eliminates the need of finding an accurate context when verifying each individual component, although such a context is still highly desirable. This method is also enhanced with additional state space reduction techniques. The experiments on several nontrivial asynchronous designs show that this method efficiently removes impossible behaviors from each component including ones violating correctness requirements.
Formal methods, model checking, modular verification, logic verification, circuit verification, abstraction, refinement.
T. Yoneda, H. Yao and H. Zheng, "Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement," in IEEE Transactions on Computers, vol. 59, no. , pp. 561-573, 2009.