The Community for Technology Leaders
Green Image
Issue No. 03 - March (2010 vol. 59)
ISSN: 0018-9340
pp: 400-415
Rodolfo Pellizzoni , University of Illinois at Urbana-Champaign, Urbana
Marco Caccamo , University of Illinois at Urbana-Champaign, Urbana
The integration phase of real-time COTS-based systems is challenging. When multiple tasks run concurrently, the interference at the bus level between cache fetching activities and I/O peripheral transactions is significant and causes unpredictable behaviors: experimentally, we show that tasks can have computation time variance up to 46 percent in a typical embedded system. In this work, we present a theoretical framework able to model the interaction between CPU and peripherals contending for shared main memory through the Front Side Bus (FSB). We first show how to compute worst case execution time (WCET) for a task given a trace of its cache activity and given an upper bound function that models peripheral activities. Then, we show how the analysis can be extended to a multitasking environment assuming a restricted-preemption model. Finally, we introduce the novel idea of “hardware server” as a means of controlling the unpredictable behavior of COTS peripheral components.
Real-time resource management, components-off-the-shelf, WCET estimation, system integration.

R. Pellizzoni and M. Caccamo, "Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems," in IEEE Transactions on Computers, vol. 59, no. , pp. 400-415, 2009.
90 ms
(Ver 3.3 (11022016))