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Issue No.12 - December (2009 vol.58)
pp: 1682-1694
Andreas Apostolakis , University of Piraeus, Piraeus
Dimitris Gizopoulos , University of Piraeus, Piraeus
Mihalis Psarakis , University of Piraeus, Piraeus
Antonis Paschalis , University of Athens, Athens
Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to other mature and well-established testing approaches to reach higher test quality. Thus far, software-based self-test approaches presented in the literature have focused almost exclusively on uniprocessors. With the continuing prevalence of multiprocessors, the focus of such research approaches moves from the uniprocessor to the multiprocessor case. In this paper, we study the application of software-based self-testing on symmetric shared-memory multiprocessors (SMP) considering the most common interconnection architectures, shared bus and crossbar switch. We focus on the impact of the shared-memory system architecture, the cache coherence mechanisms, and the interconnection architecture on the execution time of self-test programs running on each separate core and exploit the SMP's parallelism during testing to reduce the test execution time. We propose a generic methodology that allocates the test programs and test responses into the shared on-chip memory and schedules the test routines among the cores aiming at the reduction of the total test application time, and thus, test cost, for the SMP, by increasing the execution parallelism and reducing both bus contentions and data cache invalidations. We demonstrate the proposed solutions with detailed experiments on several two-core, four-core, and eight-core SMP benchmarks based on a popular RISC benchmark processor using both the shared bus and the crossbar switch interconnection architectures.
Software-based self-test (SBST), microprocessor testing, symmetric shared-memory multiprocessors (SMP), cache coherence, shared bus, crossbar switch.
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, "Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors", IEEE Transactions on Computers, vol.58, no. 12, pp. 1682-1694, December 2009, doi:10.1109/TC.2009.118
[1] F. Corno, M. Sonza Reorda, G. Squillero, and M. Violante, “On the Test of Microprocessor IP Cores,” Proc. Design Automation and Test in Europe, pp. 209-213, 2001.
[2] L. Chen, S. Ravi, A. Raghunathan, and S. Dey, “A Scalable Software-Based Self-Test Methodology for Programmable Processors,” Proc. IEEE/ACM Design Automation Conf., pp. 548-553, 2003.
[3] N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-Based Self-Testing of Embedded Processors,” IEEE Trans. Computers, vol. 54, no. 4, pp. 461-475, Apr. 2005.
[4] A. Paschalis and D. Gizopoulos, “Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 88-99, Jan. 2005.
[5] S. Gurumurthy, S. Vasudevan, and J. Abraham, “Automatic Generation of Instruction Sequences Targeting Hard-to-Detect Structural Faults in a Processor,” Proc. IEEE Int'l Test Conf., 2006.
[6] M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan, and S. Ravi, “Systematic Software-Based Self-Testing of Pipelined Processors,” Proc. IEEE/ACM Design Automation Conf., pp. 393-398, 2006.
[7] V. Singh, M. Inoue, K. Saluja, and H. Fujiwara, “Instruction-Based Self-Testing of Delay Faults in Pipelined Processors,” IEEE Trans. VLSI Systems, vol. 14, no. 11, pp. 1203-1215, Nov. 2006.
[8] P. Parvathala, K. Maneparambil, and W. Lindsay, “FRITS-A Microprocessor Functional BIST Method,” Proc. IEEE Int'l Test Conf., pp. 590-598, 2002.
[9] M. Riley, L. Bushard, N. Chelstrom, N. Kiryu, and S. Ferguson, “Testability Features of the First-Generation Cell Processor,” Proc. IEEE Int'l Test Conf., 2005.
[10] L. Bushard, N. Chelstrom, S. Ferguson, and B. Keller, “DFT of the Cell Processor and Its Impact on EDA Test Software,” Proc. IEEE Asian Test Symp., 2006.
[11] S. Makar, T. Altinis, N. Patkar, and J. Wu, “Testing of Vega2, a Chip Multi-Processor with Spare Processors,” Proc. IEEE Int'l Test Conf., 2007.
[12] I. Parulkar, T. Ziaja, R. Pendurkar, A. D'Souza, and A. Majumdar, “A Scalable, Low Cost Design-for-Test Architecture for Ultrasparc Chip Multi-Processors,” Proc. IEEE Int'l Test Conf., 2002.
[13] P.J. Tan, T. Le, K.-H. Ng, P. Mantri, and J. Westfall, “Testing of UltraSPARC T1 Microprocessor and Its Challenges,” Proc. IEEE Int'l Test Conf., 2006.
[14] I. Bayraktaroglu, J. Hunt, and D. Watkins, “Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues,” Proc. IEEE Int'l Test Conf., 2006.
[15] K. Constantinides, O. Mutlu, T. Austin, and V. Bertacco, “Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation,” Proc. IEEE Conf. Microarchitecture (MICRO '07), 2007.
[16] O. Guzey, L.-C. Wang, and J. Bhadra, “Enhancing Signal Controllability in Functional Test-Benches through Automatic Constraint Extraction,” Proc. IEEE Int'l Test Conf., 2007.
[17] “OpenCores Projects,” www.opencores.orgprojects/, 2009.
[18] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, fourth ed. Elsevier, 2006.
[19] R.B. Cooper, Introduction to Queuing Theory. Elsevier, 1981.
[20] “Stanford Small Benchmark Suite,”, 2009.
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