Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures
Issue No. 11 - November (2009 vol. 58)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.62
Siavash Bayat-Sarmadi , Univeristy of Waterloo, Waterloo
M. Anwar Hasan , University of Waterloo, Waterloo
In this work, we consider detection of errors in polynomial, dual, and normal bases arithmetic operations. Error detection is performed by recomputing with the shifted operand method, while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, one semisystolic multiplier for each of the polynomial, dual, type I, and type II optimal normal bases is presented. The results show that for having better or similar space and time overheads compared to a number of related previous work, the multipliers have generally a higher error-detection capability, e.g., the error-detection capability of the RESO-based scheme for single and multiple stuck-at faults in a polynomial basis multiplier is 100 percent. Finally, we also comment on how RESO can be used for concurrent error correction to deal with transient faults.
Finite-field operations, concurrent error detection (CED), concurrent error correction (CEC), polynomial basis, dual basis, normal basis, pipelined architectures, systolic arrays.
Siavash Bayat-Sarmadi, M. Anwar Hasan, "Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures", IEEE Transactions on Computers, vol. 58, no. , pp. 1553-1567, November 2009, doi:10.1109/TC.2009.62