Issue No. 11 - November (2009 vol. 58)

ISSN: 0018-9340

pp: 1539-1552

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.110

Ghassem Jaberipur , Shahid Beheshti University and Institute for Research in Fundamental Sciences, Tehran

Amir Kaivani , Shahid Beheshti University, Tehran

ABSTRACT

Hardware support for decimal computer arithmetic is regaining popularity. One reason is the recent growth of decimal computations in commercial, scientific, financial, and Internet-based computer applications. Newly commercialized decimal arithmetic hardware units use radix-10 sequential multipliers that are rather slow for multiplication-intensive applications. Therefore, the future relevant processors are likely to host fast parallel decimal multiplication circuits. The corresponding hardware algorithms are normally composed of three steps: partial product generation (PPG), partial product reduction (PPR), and final carry-propagating addition. The state of the art is represented by two recent full solutions with alternative designs for all the three aforementioned steps. In addition, PPR by itself has been the focus of other recent studies. In this paper, we examine both of the full solutions and the impact of a PPR-only design on the appropriate one. In order to improve the speed of parallel decimal multiplication, we present a new PPG method, fine-tune the PPR method of one of the full solutions and the final addition scheme of the other; thus, assembling a new full solution. Logical Effort analysis and 0.13 \mu{\rm m} synthesis show at least 13 percent speed advantage, but at a cost of at most 36 percent additional area consumption.

INDEX TERMS

Decimal computer arithmetic, parallel decimal multiplication, partial product generation and reduction, logic design.

CITATION

G. Jaberipur and A. Kaivani, "Improving the Speed of Parallel Decimal Multiplication," in

*IEEE Transactions on Computers*, vol. 58, no. , pp. 1539-1552, 2009.

doi:10.1109/TC.2009.110

CITATIONS