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Issue No.10 - October (2009 vol.58)
pp: 1398-1410
Mohamed Taher , Ain Shams University, Cairo
Tarek El-Ghazawi , The George Washington University, DC
Reconfigurable Computers (RCs), built from configurable processors can offer high performance in a wide range of applications. However, due to the limited reconfigurable resources, not all needed functionalities can be implemented at the same time, and runtime reconfiguration becomes an appealing solution. This work proposes techniques suitable for multitasking applications as well as applications that can change the course of processing in a nondeterministic fashion. In order to exploit both spatial and temporal locality simultaneously, the proposed model groups hardware functions into configuration blocks of fixed size (pages), variable size (segments), or hybrid (paged segments). Multiple blocks can be configured on a chip simultaneously. Data mining techniques are used to group related functions into blocks (pages or segments) and temporal locality is exploited through block replacement techniques. Simulation, as well as emulation using the Cray XD1 reconfigurable high-performance computer was used in the experimental study. Results show a significant improvement in performance using the proposed techniques.
Reconfigurable Computers (RCs), field programable gate arrays (FPGA), partial reconfiguration.
Mohamed Taher, Tarek El-Ghazawi, "Virtual Configuration Management: A Technique for Partial Runtime Reconfiguration", IEEE Transactions on Computers, vol.58, no. 10, pp. 1398-1410, October 2009, doi:10.1109/TC.2009.81
[1] K. Compton and S. Hauck, “Reconfigurable Computing: A Survey of Systems and Software,” ACM Computing Surveys, vol. 34, pp.171-210, 2002.
[2] T. El-Ghazawi, E. El-Araby, M. Huang, K. Gaj, V.V. Kindratenko, and D.A. Buell, “The Promise of High-Performance Reconfigurable Computing,” Computer, vol. 41, no. 2, pp. 69-76, Feb. 2008.
[3] T. El-Ghazawi, “A Scalable Heterogeneous Architecture for Reconfigurable Processing (SHARP),” Unpublished Manuscript, 1996,, Jan. 2009.
[4] Z. Li, K. Compton, and S. Hauck, “Configuration Caching Management Techniques for Reconfigurable Computing,” Proc. IEEE Symp. Field Programmable Gate Arrays (FPGAs) for Custom Computing Machines, pp. 87-96, 2000.
[5] Z. Li and S. Hauck, “Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation,” Proc. Field Programmable Gate Arrays (FPGA '02), pp. 187-195, 2002.
[6] N. Kasprzyk, J.C. Van Der Veen, and A. Koch, “Configuration Merging for Adaptive Computer Applications,” Proc. Int'l Conf. Field-Programmable Logic (FPL '05), pp. 217-222, Sept. 2005.
[7] S. Sudhir, S. Nath, and S. Goldstein, “Configuration Caching and Swapping,” Proc. 11th Int'l Conf. Field Programmable Logic (FPL '01), pp. 192-202, Aug. 2001.
[8] M. Taher and T. El-Ghazawi, “Exploiting Processing Locality through Paging Configurations in Multitasked Reconfigurable Systems,” Proc. IEEE Reconfigurable Architecture Workshop (RAW '06), pp. 8-15, Apr. 2006.
[9] R. Agarwal and R. Srikanth, “Fast Algorithm for Mining Association Rules,” Proc. 20th Int'l Conf. Very Large Databases, pp. 487-499, Sept. 1994.
[10] S. Kim, “M/M/s Queueing System Where Customers Demand Multiple Server Use,” PhD dissertation, Southern Methodist Univ., 1979.
[11] H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Concepts to Realizations,” Proc. Int'l Conf. Eng. Reconfigurable Systems and Architectures (ERSA), 2003.
[12] A.J. Van Der Steen and J.J. Dongarra, “Overview of Recent Supercomputers,” Univ. of Tennessee Computer Science Technical Report UT-CS-96-325, Apr. 1996,, Jan. 2009.
[13] Cray, Inc., Cray XD1 Datasheet. Cray, Inc., 2005.
[14] M. Taher and T. El-Ghazawi, “Fast Online Placement in FPGAs,” Proc. Dynamic Reconfigurable Systems Workshop (DRS '05), Mar. 2005.
[15] M. Hubner, C. Schuck, M. Kuhnle, and J. Becker, “New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-Time Adaptive Microelectronic Circuits,” Proc. IEEE CS Ann. Symp. Emerging VLSI Technologies and Architectures (ISVLSI '06), pp. 97-102.
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