Issue No. 10 - October (2009 vol. 58)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2009.89
Jin-Hao Tu , National Chiao Tung University, Hsinchu
Lan-Da Van , National Chiao Tung University, Hsinchu
In this paper, we propose a pipelined reconfigurable fixed-width Baugh-Wooley multiplier design framework that provides four configuration modes (CMs): n \times n fixed-width multiplier, two n/2 \times n/2 fixed-width multipliers, n/2 \times n/2 full-precision multiplier, and two n/4 \times n/4 full-precision multipliers. Furthermore, low-power schemes including gated clock and zero input techniques are employed to achieve the power-efficient pipelined reconfigurable design. The presented power-efficient pipelined reconfigurable fixed-width multiplier design not only generates a family of widely used multipliers but also leads to 10.59, 21.7, 28.84, and 31.58 percent power saving, on average, for n = 8, 16, 24, and 32, respectively, compared with that of the pipelined reconfigurable fixed-width multiplier without using the low-power schemes. On the other hand, compared with non-reconfigurable pipelined multiplier, we can save 0.81, 12.46, 17.93, and 23.2 percent power consumption, respectively, for n = 8, 16, 24, and 32.
Baugh-Wooley algorithm, full-precision multiplier, fixed-width multiplier, pipeline, power efficient, and reconfigurable.
J. Tu and L. Van, "Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers," in IEEE Transactions on Computers, vol. 58, no. , pp. 1346-1355, 2009.