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Issue No.10 - October (2009 vol.58)
pp: 1297-1306
Hongbin Sun , Xi'an Jiaotong University, Xi'an
Nanning Zheng , Xi'an Jiaotong University, Xi'an
Tong Zhang , Rensselaer Polytechnic Institute, Troy
It is almost evident that SRAM-based cache memories will be subject to a significant degree of parametric random defects if one wants to leverage the technology scaling to its full extent. Although strong multibit error-correcting codes (ECC) appear to be a natural choice to handle a large number of random defects, investigation of their applications in cache remains largely missing arguably because it is commonly believed that multibit ECC may incur prohibitive performance degradation and silicon/energy cost. By developing a cost-effective L2 cache architecture using multibit ECC, this paper attempts to show that, with appropriate cache architecture design, this common belief may not necessarily hold true for L2 cache. The basic idea is to supplement a conventional L2 cache core with several special-purpose small caches/buffers, which can greatly reduce the silicon cost and minimize the probability of explicitly executing multibit ECC decoding on the cache read critical path, and meanwhile, maintain soft error tolerance. Experiments show that, at the random defect density of 0.5 percent, this design approach can maintain almost the same instruction per cycle (IPC) performance over a wide spectrum of benchmarks compared with ideal defect-free L2 cache, while only incurring less than 3 percent of silicon area overhead and 36 percent power consumption overhead.
Cache, defect tolerant, error-correcting code.
Hongbin Sun, Nanning Zheng, Tong Zhang, "Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache", IEEE Transactions on Computers, vol.58, no. 10, pp. 1297-1306, October 2009, doi:10.1109/TC.2009.45
[1] Semiconductor Industry Assoc., The Int'l Technology Roadmap for Semiconductors (ITRS), http://www.itrs.netreports.html, 2009.
[2] N. Quach, “High Availability and Reliability in the Itanium Processor,” IEEE Micro., vol. 20, no. 5, pp. 61-69, Sept. 2000.
[3] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, fourth ed. Morgan Kaufmann, 2006.
[4] A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, and K. Chin, “Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells,” Proc. IEEE Int'l Electron Devices Meeting, pp. 659-662, 2005.
[5] L.D. Hung, H. Irie, M. Goshima, and S. Sakai, “Utilization of SECDED for Soft Error and Variation Induced Defect Tolerance in Caches,” Proc. Design, Automation & Test in Europe Conf. & Exhibition (DATE), pp. 1-6, 2007.
[6] J. Kim, N. Hardavellas, K. Mai, B. Falsafi, and J.C. Hoe, “Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding,” Proc. 40th Ann. ACM/IEEE Int'l Symp. Microarchitecture (Micro-40), pp. 197-209, 2007.
[7] S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications, second ed. Prentice Hall, 2004.
[8] C.L. Chen and M.Y. Hsiao, “Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review,” IBM J. Research and Development, vol. 28, no. 2, pp. 124-134, Mar. 1984.
[9] K. Chakraborty and P. Mazumder, Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories. Prentice Hall, 2002.
[10] K. Pagiamtzis, “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey,” IEEE J. Solid State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.
[11] M. Nicolaidis, N. Achouri, and L. Anghel, “A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies,” Proc. IEEE Very Large Scale Integration (VLSI) Test Symp., pp. 313-318, 2004.
[12] S. Wang and L. Wang, “Design of Error-Tolerant Cache Memory for Multithreaded Computing,” Proc. IEEE Int'l Symp. Circuits and Systems, pp. 1890-1893, May 2008.
[13] G. Di Natale, A. Benso, S. Chiusano, and P. Prinetto, “An Online BIST RAM Architecture with Self-Repair Capabilities,” IEEE Trans. Reliability, vol. 51, no. 1, pp. 123-128, Mar. 2002.
[14] CACTI: An Integrated Cache and Memory Access Time, Cycle Time, Area, Leakage, and Dynamic Power Model,, 2009.
[15] S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications. Prentice Hall, 1983.
[16] M.H. Tehranipour, Z. Navabi, and S.M. Falkhrai, “An Efficient BIST Method for Testing of Embedded SRAMs,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), pp. 73-76, May 2001.
[17] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-In Self-Test for GHz Embedded SRAMs Using Flexible Pattern Generator and New Repair Algorithm,” Proc. Int'l Test Conf., pp. 301-310, 1999.
[18] L.D. Hung et al., “Mitigating Soft Errors in Highly Associative Cache with CAM-Based Tag,” Proc. IEEE Int'l Conf. Computer Design, pp. 342-347, Oct. 2005.
[19] K. Pagiamtzis, N. Azizi, and F.N. Najm, “A Soft-Error Tolerant Content-Addresable Memory (CAM) Using an Error-Correcting-Match Scheme,” Proc. IEEE Custom Integrated Circuits Conf., pp.301-304, 2006.
[20] H.-J. Lee, “Immediate Soft Error Detection Using Pass Gate Logic for Content Addressable Memory,” Electronics Letters, vol. 44, no. 4, pp. 269-270, Feb. 2008.
[21] http:/, 2008.
[22] R.E. Blahut, Algebraic Codes for Data Transmission. Cambridge Univ. Press, 2003.
[23] Standard Performance Evaluation Corporation, http:/www.spec. org, 2000.
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