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Issue No. 09 - September (2009 vol. 58)
ISSN: 0018-9340
pp: 1171-1184
Shuai Wang , New Jersey Institute of Technology, Newark
Jie Hu , New Jersey Institute of Technology, Newark
Sotirios G. Ziavras , New Jersey Institute of Technology, Newark
Soft errors induced by energetic particle strikes in on-chip cache memories have become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have exploited information redundancy via parity/ECC codings or cacheline duplication for information integrity in on-chip cache memories. Due to various performance, area/size, and energy constraints in various target systems, many existing unoptimized protection schemes may eventually prove significantly inadequate and ineffective. In this paper, we propose a new framework for conducting comprehensive studies and characterization on the reliability behavior of cache memories, in order to provide insight into cache vulnerability to soft errors as well as design guidance to architects for highly efficient reliable on-chip cache memory design. Our work is based on the development of new lifetime models for data and tag arrays residing in both the data and instruction caches. Those models facilitate the characterization of cache vulnerability of stored items at various lifetime phases. We then exemplify this design methodology by proposing reliability schemes targeting at specific vulnerable phases. Benchmarking is carried out to showcase the effectiveness of our approach.
Cache, reliability, soft error, temporal vulnerability factor.

S. Wang, J. Hu and S. G. Ziavras, "On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors," in IEEE Transactions on Computers, vol. 58, no. , pp. 1171-1184, 2009.
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