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Issue No.03 - March (2009 vol.58)

pp: 322-335

Liang-Kai Wang , AMD, Austin

Michael J. Schulte , University of Wisconsin-Madison, Madison

John D. Thompson , Cray Inc., Chippewa Falls

Nandini Jairam , Intel Corporation, Folsom

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.147

ABSTRACT

Decimal arithmetic is often used in commercial, financial, and Internet-based applications. Due to the growing importance of decimal floating-point (DFP) arithmetic, the IEEE 754 Draft Standard for Floating-Point Arithmetic (IEEE P754) includes specifications for DFP arithmetic. This paper gives an overview of DFP arithmetic in IEEE P754 and discusses previous research on decimal fixed-point and floating-point addition. It also presents novel designs for a DFP adder and a DFP multifunction unit (DFP MFU) that comply with IEEE P754. To reduce their delay, the DFP adder and MFU both use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed DFP adder is roughly 21% faster and 1.6% smaller than a previous DFP adder design, when implemented in the same technology. Compared to the DFP adder, the DFP MFU provides six additional operations, yet only has 2.8% more delay and 9.7% more area. A pipelined version of the DFP MFU has a latency of six cycles, a throughput of one result per cycle, an estimated critical path delay of 12.9 fanout-offour (FO4) inverter delays, and an estimated area of 0.2953mm2.

INDEX TERMS

Arithmetic and logic units, Computer arithmetic, Algorithms, High-Speed Arithmetic, Arithmetic and Logic Structures, Hardware

CITATION

Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam, "Hardware Designs for Decimal Floating-Point Addition and Related Operations",

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