Issue No. 02 - February (2009 vol. 58)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.110
Karl Papadantonakis , Myricom, Arcadia
Nachiket Kapre , CALTECH, Pasadena
Stephanie Chan , Numerica Corp., Loveland
André DeHon , University of Pennsylvania, Philadelphia
Aggressive pipelining and spatial parallelism allow integrated circuits (e.g., custom VLSI, ASICs, and FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit parallelism and reduce the efficiency and speed of an implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280 MHz on a Xilinx Spartan-3 (XC3S-5000-4) FPGA, the maximum frequency supported by the component's DCM.
High-speed arithmetic, pipeline and parallel arithmetic and logic structures, saturated arithmetic, accumulation, parallel prefix.
Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon, "Pipelining Saturated Accumulation", IEEE Transactions on Computers, vol. 58, no. , pp. 208-219, February 2009, doi:10.1109/TC.2008.110