Issue No. 02 - February (2009 vol. 58)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.203
Dimitri Tan , Advanced Micro Devices Inc., Austin
Carl E. Lemonds , Advanced Micro Devices Inc., Austin
Michael J. Schulte , University of Wisconsin-Madison, Madison
The demand for improved SIMD floating-point performance on general-purpose x86-compatible microprocessors is rising. At the same time, there is a conflicting demand in the low-power computing market for a reduction in power consumption. Along with this, there is the absolute necessity of backward compatibility for x86-compatible microprocessors, which includes the support of x87 scientific floating-point instructions. The combined effect is that there is a need for low-power, low-cost floating-point units that are still capable of delivering good SIMD performance while maintaining full x86 functionality. This paper presents the design of an x86-compatible floating-point multiplier (FPM) that is compliant with the IEEE-754 Standard for Binary Floating-Point Arithmetic  and is specifically tailored to provide good SIMD performance in a low-cost, low-power solution while maintaining full x87 backward compatibility. The FPM efficiently supports multiple precisions using an iterative rectangular multiplier. The FPM can perform two parallel single-precision multiplies every cycle with a latency of two cycles, one double-precision multiply every two cycles with a latency of four cycles, or one extended-double-precision multiply every three cycles with a latency of five cycles. The iterative FPM also supports division, square-root, and transcendental functions. Compared to a previous design with similar functionality, the proposed iterative FPM has 60 percent less area and 59 percent less dynamic power dissipation.
Computer arithmetic, rectangular multiplier, floating-point arithmetic, low-power, multiplying circuits, multimedia, very-large-scale integration.
C. E. Lemonds, M. J. Schulte and D. Tan, "Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support," in IEEE Transactions on Computers, vol. 58, no. , pp. 175-187, 2008.