Issue No. 12 - December (2008 vol. 57)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.89
Junqing Sun , University of Tennessee, Knoxville
Gregory D. Peterson , University of Tennessee, Knoxville
Olaf O. Storaasli , Oak Ridge National Laboratory, Knoxville
Compared to higher-precision data formats, lower-precision data formats result in higher performance for computational intensive applications on FPGAs because of their lower resource cost, reduced memory bandwidth requirements, and higher circuit frequency. On the other hand, scientific computations usually demand highly accurate solutions. This paper seeks to utilize lower-precision data formats whenever possible for higher performance without losing the accuracy of higher-precision data formats by using mixed-precision algorithms and architectures. First, we analyze the floating-point performance of different data formats on FPGAs. Second, we introduce mixed-precision iterative refinement algorithms for linear solvers and give error analysis. Finally, we propose an innovative architecture for a mixed-precision direct solver for reconfigurable computing. Our results show that our mixed-precision algorithm and architecture significantly improve the performance of linear solvers on FPGAs.
Cost/performance, VLSI, Computer arithmetic, Multiple precision arithmetic, mixed precision arithmetic in reconfigurable computing
O. O. Storaasli, G. D. Peterson and J. Sun, "High-Performance Mixed-Precision Linear Solver for FPGAs," in IEEE Transactions on Computers, vol. 57, no. , pp. 1614-1623, 2008.