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Issue No. 09 - September (2008 vol. 57)
ISSN: 0018-9340
pp: 1196-1201
Francesco Vitullo , University of Pisa, Pisa
Nicola E. L'Insalata , University of Pisa, Pisa
Esa Petri , University of Pisa, Pisa
Sergio Saponara , University of Pisa, Pisa
Luca Fanucci , University of Pisa, Pisa
Michele Casula , University of Pisa, Pisa
Riccardo Locatelli , STMicroelectronics, Grenoble
Marcello Coppola , STMicroelectronics, Grenoble
ABSTRACT
Clock distribution is an important issue when designing Multi Processor Systems-on-Chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a Multi Processor tiled architecture based on a Network-on-Chip communication backbone on a CMOS 65 nm technology
INDEX TERMS
On-chip interconnection networks, Asynchronous/synchronous operation, Register-Transfer-Level Implementation, Multiprocessor Systems, Standard cells, VLSI Systems, Low-power design, VLSI, Architecture
CITATION

R. Locatelli et al., "Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip," in IEEE Transactions on Computers, vol. 57, no. , pp. 1196-1201, 2008.
doi:10.1109/TC.2008.48
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