Issue No. 09 - September (2008 vol. 57)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2008.77
Avinash Karanth Kodi , University of Arizona, Tucson
Ashwini Sarathy , University of Arizona, Tucson
Ahmed Louri , University of Arizona, Tucson
Recent research in On-chip interconnection networks (OCINs) research has shown that the design of buffers in the router significantly influences the power, area overhead and overall performance of the network. In this paper, we propose a low-power, low-area OCIN architecture by reducing the number of buffers within the router. To minimize the performance degradation due to the reduced buffer size, we use the existing repeaters along the inter-router channels to double as buffers when required. At low network loads, the proposed adaptive channel buffers function as conventional repeaters propagating the signals. At high network loads, the adaptive channel buffers function as storage elements in addition to the router buffers. We evaluate the proposed adaptive channel buffers with both static and dynamic buffer allocation policies in the 90nm technology node, using 8?8 mesh and folded torus network topologies. Simulation results using the SPLASH-2 suite and synthetic traffic show that by reducing the router buffer size our proposed architecture achieves nearly 40% savings in router buffer power, 30% savings in overall network power and 40% savings in area, with only a marginal 1-5% drop in throughput under dynamic buffer allocation and about 10-20% drop in throughput for statically assigned buffers.
On-chip interconnection networks, Interconnection architectures, Low-power design
A. K. Kodi, A. Louri and A. Sarathy, "Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis," in IEEE Transactions on Computers, vol. 57, no. , pp. 1169-1181, 2008.