The Community for Technology Leaders
Green Image
TABLE OF CONTENTS
Issue No. 09 - September (vol. 57)
ISSN: 0018-9340
Special Section on Networks-on-Chip

Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks (Abstract)

Shu-Yen Lin , Nat. Taiwan Univ., Taipei
Chun-Hsiang Huang , Nat. Taiwan Univ., Taipei
Chih-Hao Chao , Nat. Taiwan Univ., Taipei
Keng-Hsien Huang , Nat. Taiwan Univ., Taipei
An-Yeu Wu , Nat. Taiwan Univ., Taipei
pp. 1156-1168
Special Section on Networks-on-Chip

Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks (Abstract)

Keng-Hsien Huang , National Taiwan University, Taipei
An-Yeu (Andy) Wu , National Taiwan University, Taipei
Shu-Yen Lin , National Taiwan University, Taipei
Chun-Hsiang Huang , National Taiwan University, Taipei
pp. 1156-1168

Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis (Abstract)

Avinash Karanth Kodi , University of Arizona, Tucson
Ahmed Louri , University of Arizona, Tucson
Ashwini Sarathy , University of Arizona, Tucson
pp. 1169-1181

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip (Abstract)

Dragomir Milojevic , Université Libre de Bruxelles, Bruxelles
Frédéric Robert , Université Libre de Bruxelles, Bruxelles
Anthony Leroy , Université Libre de Bruxelles, Bruxelles
Francky Catthoor , Inter-university Micro-Electronics Center, Heverlee, Belgium
Diederik Verkest , Katholieke Universiteit Leuven, Belgium
pp. 1182-1195

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip (Abstract)

Riccardo Locatelli , STMicroelectronics, Grenoble
Michele Casula , University of Pisa, Pisa
Francesco Vitullo , University of Pisa, Pisa
Luca Fanucci , University of Pisa, Pisa
Nicola E. L'Insalata , University of Pisa, Pisa
Marcello Coppola , STMicroelectronics, Grenoble
Sergio Saponara , University of Pisa, Pisa
Esa Petri , University of Pisa, Pisa
pp. 1196-1201

Secure Memory Accesses on Networks-on-Chip (Abstract)

Cristina Silvano , Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Slobodan Lukovic , ALaRI, Faculty of Informatics, University of Lugano, Lugano
Leandro Fiorin , ALaRI, Faculty of Informatics, University of Lugano, Lugano
Gianluca Palermo , Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy
Valerio Catalano , ST Microelectronics, AST Grenoble Lab, France
pp. 1216-1229

SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip (Abstract)

Dan Zhao , University of Louisiana at Lafayette, Lafayeette
Yi Wang , University of Louisiana at Lafayette, Lafayette
pp. 1230-1245

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (Abstract)

Assaf Shacham , Columbia University, New York
Keren Bergman , Columbia University, New York
Luca P. Carloni , Columbia University, New York
pp. 1246-1260
Regular Papers

Efficient Exact Schedulability Tests for Fixed Priority Real-Time Systems (Abstract)

Attila Zabos , University of York, York
Alan Burns , University of York, York
Robert I. Davis , University of York, York
pp. 1261-1276

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model (Abstract)

Wei Huang , University of Virginia, Charlottesville
Mircea R. Stan , University of Virginia, Charlottesville
Karthik Sankaranarayanan , University of Virginia, Charlottesville
Kevin Skadron , University of Virginia, Charlottesville
Robert J. Ribando , University of Virginia, Charlottesville
pp. 1277-1288
Brief Contributions

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m) (Abstract)

Dhiraj K. Pradhan , University of Bristol, Bristol
Hafizur Rahaman , University of Bristol, Bristol
Jimson Mathew , University of Bristol, Bristol
Abusaleh M. Jabir , University of Bristol, Bristol
pp. 1289-1294
98 ms
(Ver )