The Community for Technology Leaders
RSS Icon
Issue No.08 - August (2008 vol.57)
pp: 1012-1022
Ioannis Voyiatzis , Technological Educational Institute of Athens, Athens
Antonis Paschalis , University of Athens, Athens
Dimitris Gizopoulos , University of Piraeus, Piraeus
Constantin Halatsis , University of Athens, Athens
Frosso S. Makri , University of Patras, Patras
Miltiadis Hatzimihail , University of Piraeus, Piraeus
Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.
On-Line Testing, Off-Line Testing, Self-Testing, Input Vector Monitoring Concurrent Error Detection, Pre-Computed Test Set
Ioannis Voyiatzis, Antonis Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail, "An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set", IEEE Transactions on Computers, vol.57, no. 8, pp. 1012-1022, August 2008, doi:10.1109/TC.2008.49
[1] M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[2] K.K. Saluja, R. Sharma, and C.R. Kime, “A Concurrent Testing Technique for Digital Circuits,” IEEE Trans. Computer-Aided Design, vol. 7, no. 12, p. 1259, Dec. 1988.
[3] K.K. Saluja, R. Sharma, and C.R. Kime, “Concurrent Comparative Testing Using BIST Resources,” Proc. Int'l Conf. Computer Aided Design, pp. 336-339, Nov. 1987.
[4] K.K. Saluja, R. Sharma, and C.R. Kime, “Concurrent Comparative Built-In Testing of Digital Circuits,” Technical Report ECE-8711, Dept. of Electrical and Computer Eng., Univ. of Wisconsin, 1986.
[5] I. Voyiatzis and C. Halatsis, “A Low Cost Concurrent BIST Scheme for Increased Dependability,” IEEE Trans. Dependable and Secure Computing, vol. 2, no. 2, Apr.-June 2005.
[6] I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, and C. Halatsis, “A Concurrent Built-In Self Test Architecture Based on a Self-Testing RAM,” IEEE Trans. Reliability, vol. 54, no. 1, pp. 69-78, Mar. 2005.
[7] R. Sharma and K.K. Saluja, “Theory, Analysis and Implementation of an On-Line BIST Technique,” VLSI Design, vol. 1, no. 1, pp.9-22, 1993.
[8] J. Rajski and J. Tsyzer, “Test Responses Compaction in Accumulators with Rotate Carry Adders,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 4, pp. 531-539, Apr. 1993.
[9] F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmarks Circuits and a Target Translator in FORTRAN,” Proc. Int'l Symp. Circuits and Systems, 1985.
[10] I. Pomeranz, L.N. Reddy, and S.M. Reddy, “COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits,” Proc. Int'l Test Conf., pp. 194-203, Oct. 1991.
[11] K. Chakrabarty, “Zero-Aliasing Space Compaction Using Linear Compactors with Bounded Overhead,” IEEE Trans. CAD/ICAS, vol. 17, pp. 452-457, May 1998.
[12] K. Chakrabarty and J.P. Hayes, “Zero-Aliasing Space Compaction Using Multiple Parity Signatures,” IEEE Trans. VLSI Systems, vol. 6, pp. 309-313, June 1998.
[13] K. Chakrabarty, B.T. Murray, and J.P. Hayes, “Optimal Zero-Aliasing Space Compaction of Test Responses,” IEEE Trans. Computers, vol. 47, no. 11, pp. 1171-1187, Nov. 1998.
[14] K. Chakrabarty and M. Seuring, “Space Compaction of Test Responses Using Orthogonal Transmission Functions,” IEEE Trans. Instrumentation and Measurement, vol. 52, pp. 1353-1362, Oct. 2003.
[15] N. Mukherjee and R. Karri, “Versatile BIST: An Integrated Approach to On-Line/Off-Line BIST for Data-Dominated Architectures,” J. Electronic Testing, vol. 13, no. 2, pp. 189-200(12), Oct. 1998.
[16] X. Sun and M. Serra, “Design and Implementation of a Merged On-Line and Off-Line Self Testable Architecture,” Proc. IEEE Int'l Workshop Defect and Fault Tolerance in VLSI Systems, pp. 247-254, Oct. 1993.
[17] H. Al-Asaad and M. Shringi, “On-Line Built-In Self-Test for Operational Faults,” Proc. Systems Readiness Technology Conf., pp.168-174, 2000.
[18] M. Chatterjee and D.K. Pradhan, “A BIST Pattern Generator Design for Near-Perfect Fault Coverage,” IEEE Trans. Computers, vol. 52, no. 12, Dec. 2003.
[19] C. Fagot, O. Gascuel, P. Girard, and C. Landrault, “A Ring Architecture Strategy for BIST Test Pattern Generation,” J.Electronic Testing: Theory and Applications, vol. 19, pp. 223-231, 2003.
[20] M. Abramovici, C.E. Stroud, and J.M. Emmert, “Online BIST and BIST-Based Diagnosis of FPGA Logic Blocks,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 12, pp. 1284-1294, Dec. 2004.
[21] A. Steininger and J. Vilanek, “Using Offline and Online BIST to Improve System Dependability—The TTPC-C Example,” Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 277-280, 2002.
[22] H. Al-Asaad, B.T. Murray, and J.P. Hayes, “Online BIST for Embedded Systems,” IEEE Design and Test of Computers, vol. 15, no. 4, pp. 17-24, Oct.-Dec. 1998.
[23] C. Scherrer and A. Steininger, “On the Necessity of On-Line-BIST in Safety-Critical Applications—A Case Study,” Proc. 29th Ann. Int'l Symp. Fault-Tolerant Computing, p. 208, 1999.
[24] H. Al-Asaad, J.P. Hayes, and B.T. Murray, “Design of Scalable Hardware Test Generators for On-Line BIST,” Proc. IEEE Int'l On-Line Testing Workshop, pp. 164-167, 1996.
[25] M. Abramovici, C. Stroud, B. Skaggs, and J. Emmert, “Improving On-Line BIST-Based Diagnosis for Roving STARs,” Proc. Sixth IEEE Int'l On-Line Testing Workshop, p. 31, 2000.
[26] M. Pflanz, K. Walther, C. Galke, and H.T. Vierhaus, “On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check,” J. Electronic Testing: Theory and Applications, vol. 19, pp. 501-510, 2003.
[27] M. Nicolaidis and Y. Zorian, “On-Line Testing for VLSI-A Compendium of Approaches,” J. Electronic Testing: Theory and Applications, vol. 12, nos. 1-2, pp. 7-20, Feb.-Apr. 1998.
[28] B.W. Johnson, Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley, 1989.
28 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool