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Issue No. 08 - August (2008 vol. 57)
ISSN: 0018-9340
pp: 1012-1022
Miltiadis Hatzimihail , University of Piraeus, Piraeus
Constantin Halatsis , University of Athens, Athens
Antonis Paschalis , University of Athens, Athens
Frosso S. Makri , University of Patras, Patras
Dimitris Gizopoulos , University of Piraeus, Piraeus
Ioannis Voyiatzis , Technological Educational Institute of Athens, Athens
ABSTRACT
Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.
INDEX TERMS
On-Line Testing, Off-Line Testing, Self-Testing, Input Vector Monitoring Concurrent Error Detection, Pre-Computed Test Set
CITATION
Miltiadis Hatzimihail, Constantin Halatsis, Antonis Paschalis, Frosso S. Makri, Dimitris Gizopoulos, Ioannis Voyiatzis, "An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set", IEEE Transactions on Computers, vol. 57, no. , pp. 1012-1022, August 2008, doi:10.1109/TC.2008.49
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