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Issue No.06 - June (2008 vol.57)
pp: 809-820
Giuseppe Ascia , University of Catania
Vincenzo Catania , University of Catania
Maurizio Palesi , University of Catania
Davide Patti , University of Catania
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. A selection function is used to select the output channel where the packet will be forwarded on. In this paper we present a novel selection strategy that can be coupled with any adaptive routing algorithm. The proposed selection strategy is based on the concept of Neighbors-on-Path the aims of which is to exploit the situations of indecision occurring when the routing function returns several admissible output channels. The overall objective is to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator under traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection strategy applied to the Odd-Even routing algorithm yields an improvement in both average delay and saturation point up to 20% and 30% on average respectively, with a minimal overhead in terms of area occupation. In addition, a positive effect on total energy consumption is also observed under near-congestion packet injection rates.
Interconnection architectures, Routing protocols, Performance evaluation
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, "Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip", IEEE Transactions on Computers, vol.57, no. 6, pp. 809-820, June 2008, doi:10.1109/TC.2008.38
[1] A. Ivanov and G.D. Micheli, “The Network-on-Chip Paradigm in Practice and Research,” IEEE Design and Test of Computers, vol. 22, no. 5, pp. 399-403, Sept./Oct. 2005.
[2] “International Technology Roadmap for Semiconductors—Interconnect,” Semiconductor Industry Assoc., 2006.
[3] “On-Chip Bus Attributes Specification Version 1,” VSI Alliance, http:/, Sept. 2001.
[4] “The CoreConnect Bus Architecture,” IBM, http:/ com/, 2008.
[5] “AMBA Specification,” ARM, http:/, May 1999.
[6] “SoC Bus Architecture,” Palmchip, http:/, 2008.
[7] “WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores,” Silicore, http:/, Sept. 2002.
[8] “SiliconBackplane III MicroNetwork IP,” Sonics, http:/www., 2008.
[9] Networks on Chip, A. Jantsch and H. Tenhunen, eds., ch. 1. Kluwer Academic, 2003.
[10] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proc. ACM/IEEE Design Automation Conf., pp. 684-689, 2001.
[11] L. Schwiebert and R. Bell, “Performance Tuning of Adaptive Wormhole Routing through Selection Function Choice,” J. Parallel and Distributed Computing, vol. 62, no. 7, pp. 1121-1141, July 2002.
[12] W.C. Feng and K.G. Shin, “Impact of Selection Functions on Routing Algorithm Performance in Multicomputer Networks,” Proc. 11th Int'l Conf. Supercomputing, pp. 132-139, 1997.
[13] J.C. Martínez, F. Silla, P. López, and J. Duato, “On the Influence of the Selection Function on the Performance of Networks of Workstations,” Proc. Int'l Symp. High Performance Computing, pp.292-299, 2000.
[14] P. Mohapatra, “Wormhole Routing Techniques for Directly Connected Multicomputer Systems,” ACM Computing Surveys, vol. 30, no. 8, pp. 374-410, Sept. 1998.
[15] J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2002.
[16] G.-M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000.
[17] D. Linder and J. Harden, “An Adaptive and Fault-Tolerant Wormhole Routing Strategy for k-Ary n-Cubes,” IEEE Trans. Computers, vol. 40, no. 1, pp. 2-12, Jan. 1991.
[18] C.J. Glass and L.M. Ni, “The Turn Model for Adaptive Routing,” J.ACM, vol. 41, no. 5, pp. 874-902, Sept. 1994.
[19] A.A. Chien and J.H. Kim, “Planar-Adaptive Routing: Low-Cost Adaptive Networks for Multiprocessors,” J. ACM, vol. 42, no. 1, pp. 91-123, Jan. 1995.
[20] J. Upadhyay, V. Varavithya, and P. Mohapatra, “A Traffic-Balanced Adaptive Wormhole Routing Scheme for Two-Dimensional Meshes,” IEEE Trans. Computers, vol. 46, no. 2, pp. 190-197, Feb. 1997.
[21] E. Bolotin, A. Morgenshtein, I. Cidon, and A. Kolodny, “Automatic and Hardware-Efficient SoC Integration by QoS Network on Chip,” Proc. IEEE Int'l Conf. Electronics, Circuits and Systems, Dec. 2004.
[22] R. Holsmark and S. Kumar, “Design Issues and Performance Evaluation of Mesh NoC with Regions,” Proc. IEEE Norchip, pp.40-43, Nov. 2005.
[23] M. Li, Q.-A. Zeng, and W.-B. Jone, “DyXY—A Proximity Congestion-Aware Deadlock-Free Dynamic Routing Method for Networks on Chip,” Proc. ACM/IEEE Design Automation Conf., pp.849-852, July 2006.
[24] M. Palesi, R. Holsmark, S. Kumar, and V. Catania, “A Methodology for Design of Application Specific Deadlock-Free Routing Algorithms for NoC Systems,” Proc. Int'l Conf. Hardware-Software Codesign and System Synthesis, pp. 142-147, Oct. 2006.
[25] M.D. Schroeder, A.D. Birrell, M. Burrows, H. Murray, R.M. Needham, T.L. Rodeheffer, E.H. Satterthwaite, and C.P. Thacker, “Autonet: A High-Speed, Self-Configuring Local Area Network Using Point-to-Point Links,” Technical Report 59, Digital Equipment, Apr. 1990.
[26] A. Jouraku, M. Koibuchi, and H. Amano, “L-Turn Routing: An Adaptive Routing in Irregular Networks,” Technical Report 59, IEICE, Apr. 2001.
[27] L. Cherkasova, V. Kotov, and T. Rokicki, “Fibre Channel Fabrics: Evaluation and Design,” Proc. Hawaii Int'l Conf. System Sciences, pp. 53-58, 1996.
[28] J.C. Sancho, A. Robles, and J. Duato, “A Flexible Routing Scheme for Networks of Workstations,” Proc. Int'l Symp. High Performance Computing, pp. 260-267, 2000.
[29] A. Mejia, J. Flich, J. Duato, S.-A. Reinemo, and T. Skeie, “Segment-Based Routing: An Efficient Fault-Tolerant Routing Algorithm for Meshes and Tori,” Proc. Int'l Parallel and Distributed Processing Symp., Apr. 2006.
[30] J. Hu and R. Marculescu, “DyAD—Smart Routing for Networks-on-Chip,” Proc. ACM/IEEE Design Automation Conf., pp. 260-263, June 2004.
[31] T.T. Ye, L. Benini, and G.D. Micheli, “Packetization and Routing Analysis of On-Chip Multiprocessor Networks,” J. System Architectures, vol. 50, nos. 2-3, pp. 81-104, 2004.
[32] E. Nilsson, M. Millberg, J. Oberg, and A. Jantsch, “Load Distribution with the Proximity Congestion Awareness in a Network on Chip,” Proc. Design, Automation and Test in Europe, pp. 1126-1127, 2003.
[33] D. Wu, B.M. Al-Hashimi, and M.T. Schmitz, “Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection,” Proc. Asia and South Pacific Design Automation Conf., pp.36-41, 2006.
[34] “Noxim: Network-on-Chip Simulator,”, 2008.
[35] J. Hu and R. Marculescu, “Energy- and Performance-Aware Mapping for Regular NoC Architectures,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp.551-562, Apr. 2005.
[36] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
[37] G. Ascia, V. Catania, and M. Palesi, “Multi-Objective Mapping for Mesh-Based NoC Architectures,” Proc. Second IEEE/ACM/IFIP Int'l Conf. Hardware/Software Codesign and System Synthesis, pp. 182-187, Sept. 2004.
[38] G. Varatkar and R. Marculescu, “Traffic Analysis for On-Chip Networks Design of Multimedia Applications,” Proc. ACM/IEEE Design Automation Conf., pp. 510-517, June 2002.
[39] P.P. Pande, C. Grecu, and I. Ivanov, “High-Throughput Switch-Based Interconnect for Future SoCs,” Proc. IEEE Int'l Workshop System-on-Chip for Real-Time Applications, pp. 304-310, 2003.
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