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Word-organized memories are typically tested by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intra-word fault model), resulting in limited fault coverage. In this paper a new approach for testing word-organized memories is presented, that systematically converts tests for bit-organized memories to tests for word-organized memories. The implementation of the proposed scheme in hardware is based on an ALU whose inputs are driven by a barrel shifter. Since such modules commonly exist in current chips, the hardware overhead of the scheme is extremely low.
Semiconductor Memories, Reliability, Testing and Fault-Tolerance, Test generation, Built-In Tests, Memory control and access

I. Voyiatzis, "An ALU-Based BIST Scheme for Word-Organized RAMs," in IEEE Transactions on Computers, vol. 57, no. , pp. 577-590, 2007.
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