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Issue No.04 - April (2008 vol.57)
pp: 532-546
In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realised? Herein we describe the European Logarithmic Microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful; that for 32-bit work logarithmic arithmetic may now be the technique of choice.
High-Speed Arithmetic, General
John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichy, Z. Pohl, Antonin Hermanek, Nico F. Benschop, "The European Logarithmic Microprocesor", IEEE Transactions on Computers, vol.57, no. 4, pp. 532-546, April 2008, doi:10.1109/TC.2007.70791
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