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Issue No.04 - April (2008 vol.57)
pp: 505-519
A communication scheme in which symbols are encoded by means of phase difference between transitions of signals on parallel wires is considered. A significant decrease in the reliability of such a channel is caused by capacitive crosstalk between adjacent wires. A more robust high-speed phase encoded channel can be designed by minimising its vulnerability to crosstalk noise. This paper investigates the impact of crosstalk on phase encoded transmission channels. A functional fault model is presented to formulate the problem. Three fault tolerant schemes are introduced which are based on information redundancy techniques and the partial order coding concept. These schemes are simulated with CADENCE using AMS CMOS 0.35?m process. Area overheads, performance and fault tolerant capability of those methods are compared. It is shown that a substantial improvement in the performance can be obtained for four wire channels when using the fault tolerant design approach, at the cost of 25% of information capacity per symbol.
Asynchronous operation, crosstalk, communication channels, Error-checking, Fault tolerance, information redundancy, Simulation, Performance, reliability and VLSI
Basel Halak, Alex Yakovlev, "Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels", IEEE Transactions on Computers, vol.57, no. 4, pp. 505-519, April 2008, doi:10.1109/TC.2007.70825
[1] F. Caignet, S. Delmas-Bendhia, and E. Sicard, “The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology,” Proc. IEEE, vol. 89, pp. 490-504, 2001.
[2] D. Pamunuwa, L.R. Zheng, and H. Tenhunen, “Maximizing Throughput over Parallel Wire Structures in the Deep Sub Micrometer Regime,” IEEE Trans. VLSI Systems, vol. 11, pp. 224-243, Apr. 2003.
[3] N.A. Kurd et al., “Multi-GHz Clocking Scheme for Intel Pentium 4 Microprocessor,” Proc. IEEE Int'l Solid-State Circuits Conf., pp. 404-405, Feb. 2001.
[4] D.M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems,” PhD dissertation, Stanford Univ., Calif., 1984.
[5] International Technology Roadmap for Semiconductors (ITRS-2005), chapter on design, 2005.
[6] A. Chakraborty and M.R. Greenstreet, “Efficient Self-Timed Interfaces for Crossing Clock Domains,” Proc. Ninth IEEE Int'l Symp. Asynchronous Circuits and Systems, 2003.
[7] W.J. Bainbridge, W.B. Toms, D.A. Edwards, and S.B. Furber, “Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes,” Proc. Ninth IEEE Int'l Symp. Asynchronous Circuits and Systems, 2003.
[8] C. D'Alessandro, D. Shang, A. Bystrov, and A. Yakovlev, “PSK Signalling on SoC Buses,” Proc. 15th Int'l Workshop Power and Timing Modeling, Optimization and Simulation, 2005.
[9] E. Dupont, M. Nicolaidis, and P. Rohr, “Embedded Robustness Ips,” Proc. Design, Automation and Test in Europe Conf. and Exposition, 2002.
[10] M. Nicolaidis, “Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies,” Proc. 17th IEEE VLSI Test Symp., Apr. 1999.
[11] D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, “Design and Analysis of Dual Rail Circuits for Security Applications,” IEEE Trans. Computers, vol. 54, no. 4, pp. 449-460, Apr. 2005.
[12] C. D'Alessandro, D. Shang, A. Bystrov, A. Yakovlev, and O. Maevsky, “Multiple-Rail Phase-Encoding for NoC,” Proc. 12th IEEE Int'l Symp. Asynchronous Circuits and Systems, 2006.
[13] C.E. Molnar and I.W. Jones, “Simple Circuits that Work for Complicated Reasons,” Proc. Sixth IEEE Int'l Symp. Asynchronous Circuits and Systems, 2000.
[14] J.M. Rabaey, Digital Integrated Circuits. Prentice Hall, 2003.
[15] P.P. Sotiriadis and A. Chandrakasan, “Reducing Bus Delay in Submicron Technology Using Coding,” Proc. Asia and South Pacific Design Automation Conf., pp. 109-114, 2001.
[16] S.R. Sridhara, A. Ahmed, and N.R. Shanbhag, “Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses,” Proc. 22nd IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 12-17, 2004.
[17] S. Muddu et al., “Repeater and Interconnect Strategies for High-Performance Physical Designs,” Proc. IEEE Brazilian Symp. Integrated Circuit Design, 1998.
[18] D. Pamunuwa and H. Tenhunen, “Repeater Insertion to Minimise Delay in Coupled Interconnects,” Proc. 14th Int'l Conf. VLSI Design, 2001.
[19] D. Rossi, C. Metra, A.K. Nieuwland, and A. Katoch, “Exploiting ECC Redundancy to Minimize Crosstalk Impact,” IEEE Design and Test of Computers, vol. 22, no. 1, pp. 59-70, Jan./Feb. 2005.
[20] B. Victor and K. Keutzer, “Bus Encoding to Prevent Crosstalk Delay,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 57-63, 2001.
[21] C. Duan, A. Tirumala, and S.P. Khatri, “Analysis and Avoidance of Cross-Talk in On-Chip Buses,” Proc. Hot Interconnects 9, pp. 133-138, 2001.
[22] M.A. Abas, G. Russell, and D.J. Kinniment, “Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit,” Proc. Design, Automation and Test in Europe Conf. and Exposition, pp. 804-809, 2004.
[23] M.A. Abas, A. Bystrov, D.J. Kinniment, O. Maevsky, G. Russell, and A. Yakovlev, “Time Difference Amplifier,” Electronics Letters, vol. 38, no. 23, pp. 1437-1438, Nov. 2002.
[24] B. Halak and G. Russell, “The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories,” Informal Proc. European Test Symp., pp. 188-193, May 2006.
[25] G. Russell and I.L. Sayers, Advanced Simulation and Test Methodologies for VLSI Design, chapter 9, pp. 250-298, 1989.
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