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The unfolded and pipelined CORDIC is a high performance hardware element that produces a wide variety of one and two argument functions with high throughput. The reduction in delay, power, and area (cost) are of significant interest regarding this module due to its high demand for resources. The linear approach to rotation has been proposed to achieve such reductions; however, the schemes for rotation (multiplication) and vectoring (division) complicate the implementation in a single unit. In this work, we improve the linear approximation scheme, leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of CORDIC iterations. We also combine the linear approximation to rotation with the scale factor compensation so that the compensation is performed concurrently with the rotation process. We then extend the method to 3D CORDIC. Such an extension is not straightforward due to the lack of existing analytical expressions for the convergence of the algorithm. A comparison using a rough area--time model and synthesis results shows that our proposals may achieve significant reductions in delay with no increase in area in actual implementations.
Arithmetic and Logic Structures, High-Speed Arithmetic, Algorithms, Computer arithmetic
Emilio L. Zapata, Julio Villalba, Elisardo Antelo, "A Low-Latency Pipelined 2D and 3D CORDIC Processors", IEEE Transactions on Computers, vol. 57, no. , pp. 404-417, March 2008, doi:10.1109/TC.2007.70796
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