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Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (SoC) and have not been fully resolved even if a scan-based technique is employed. A novel architecture referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuitunder-test (CUT) and increases the clock frequency of the scanning process. An auxiliary chain is utilized in this architecture to avoid the large number of transitions to the CUT during the scan-in process, as well as enabling retention of the currently applied test vectors and applying only necessary changes to them. The auxiliary chain shifts in the difference between consecutive test vectors and only the required transitions (referred to as trigger data) are applied to the CUT. Power requirements are substantially reduced; moreover, DFT penalties are reduced because no additional multiplexer is utilized along the scan path. Data reformatting is applied in order to make the proposed architecture amenable to data compression, thus permitting a further reduction in test time. It also permits delay fault testing. Using ISCAS 85 and 89 benchmark circuits, the effectiveness of this architecture for improving SoC test measures (such as power, time and data volume) is experimentally evaluated and confirmed.
Scan Test, Test Data Volume, Test Application Time, Test Power, Test Compression, Delay Testing

F. Lombardi, M. Hosseinabady, Z. Navabi and S. Sharifi, "A Selective Trigger Scan Architecture for VLSI Testing," in IEEE Transactions on Computers, vol. 57, no. , pp. 316-328, 2007.
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