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A set of graph augmentation algorithms are introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1-clock and n-clock timing faults, and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is in the same order of magnitude as of the original specification.
Conformance Testing, Timers, Fault Modeling, Finite State Machine (FSM), Extended Finite State Machine (EFSM), Timed EFSM.
M. Umit Uyar, Mariusz A. Fecko, Samrat S. Batth, Yu Wang, "Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols", IEEE Transactions on Computers, vol. 57, no. , pp. 274-288, February 2008, doi:10.1109/TC.2007.70772
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