The Community for Technology Leaders
Green Image
High-performance microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of such RFs mainly stem from the need to maintain each and every result for a large number of cycles after the result generation. We observed that a significant fraction (about 45%) of the result values are never read from the register file and are not required to recover from branch mispredictions. In this paper, we propose SPARTAN - a set of micro-architectural extensions that predicts such transient values and in many cases completely avoids physical register allocations to them. We show that the transient values can be predicted as such with more than 97% accuracy on the average across simulated SPEC 2000 benchmarks. We evaluate the performance of SPARTAN on a variety of configurations and show that significant improvements in performance and energy-efficiency can be realized. Furthermore, we directly compare SPARTAN against a number of previously proposed schemes for register optimizations and show that our technique significantly outperforms all those schemes.
General, Pipeline processors, Microprocessors, Performance attributes

D. Balkan, J. Sharkey, K. Ghose and D. V. Ponomarev, "Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption," in IEEE Transactions on Computers, vol. 57, no. , pp. 82-95, 2007.
99 ms
(Ver 3.3 (11022016))