Issue No. 01 - January (2008 vol. 57)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70771
Performance and power act as opposing constraints for optimal pipeline depth of a processor. While increasing the pipeline depth may enable performance improvement, the higher clock speed associated with a deeper pipeline also increases the power dissipation. As simultaneous multi-threading (SMT) becomes increasingly important for modern high-end processors, there is a need to quantify the optimal power-performance pipeline depth for SMT. While previous work has shown that SMT retains the performance-optimal pipeline depth in near-future technologies, this result does not take power into account. The intricate interplay between the relative impacts of changing pipeline depth on power and performance makes it difficult to predict the scaling trends for optimal SMT pipeline depths considering both power and performance. Using simulations, we quantify the optimal SMT pipeline depths based on the well-known power-performance metric PD3. Our analysis is novel and provides the following key results about the scaling trends for SMT pipelines considering both power and performance: (1) SMT has a deeper PD3-optimal pipeline as compared to superscalar. (2) The PD3-optimal SMT pipeline depth increases with an increase in the number of programs. (3) The PD3-optimal SMT pipeline becomes shallower with technology for a given number of programs.
Multithreaded processors, Power Management, Performance of Systems
Zeshan Chishti, T.N. Vijaykumar, "Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies", IEEE Transactions on Computers, vol. 57, no. , pp. 69-81, January 2008, doi:10.1109/TC.2007.70771