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In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits. To date, however, we have not found any work that aims at protecting the control logic of these circuits against fault attacks, which thus remains the proverbial Achilles' heel. Motivated by a hypothetical yet realistic fault analysis attack that, in principle, could be mounted against any modular exponentiation engine, even one with appropriate data path protection, we set out to close this remaining gap. In this paper, we present guidelines for the design of multifault-resilient sequential control logic based on standard Error-Detecting Codes (EDCs) with large minimum distance. We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in implementing the EDC. Our comparison shows that the proposed EDC-based technique provides superior performance when compared against regular N-modular redundancy techniques. Furthermore, our technique scales well and does not affect the critical path delay.
Circuit faults, Cryptography, Fault tolerance, Fault tolerant systems, Registers, Sequential circuits, Public key, Pipelines, and Fault-Tolerance, Hardware, Control Structure Reliability, Testing
"Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults", IEEE Transactions on Computers, vol. 57, no. , pp. 1, January 2008, doi:10.1109/TC.2007.70784
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