Issue No. 12 - December (2007 vol. 56)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2007.70766
This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.
computer architecture, embedded systems, fault tolerance, microprocessor chips, pipeline processing, probability, statistical analysis,latent fault, probability, single-dual fault injection, statistical method, automotive application, distributed voting, microarchitecture, fault-tolerant 32-bit embedded CPU, pipeline-protected microprocessor, SEU-induced fault,Circuit faults, Pipelines, Registers, Microprocessors, Fault tolerance, Fault tolerant systems,fault injection, fault modeling and simulation, SEU, soft error, microprocessor test, fault tolerance,fault injection, fault modeling and simulation, SEU, soft error, microprocessor test, fault tolerance
"Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor", IEEE Transactions on Computers, vol. 56, no. , pp. 1585-1596, December 2007, doi:10.1109/TC.2007.70766