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Novel modulo 2<sup>n</sup>-1 addition algorithms for RNS applications are presented. The proposed algorithms depart from the traditional approach of modulo 2<sup>n</sup>-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures do not only offer significant speed-up in modulo 2<sup>n</sup>-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area x delay<sup>2</sup> and energy x delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130nm CMOS technology.
Modulo 2n-1 adders, One's complement adders, parallel-prefix adders, computer arithmetic, VLSI design

M. Benaissa, S. Boussakta and R. A. Patel, "Fast Parallel-Prefix Architectures for Modulo 2<sup>n</sup>-1 Addition with a Single Representation of Zero," in IEEE Transactions on Computers, vol. 56, no. , pp. 1484-1492, 2007.
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