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<p><b>Abstract</b>—In the paper a new GF(2^m) multiplier for standard basis representation is developed. Proposed multiplier implements the Mastrovito multiplication scheme and can be designed for every field GF(2^m). A minimum area implementation of the first block of Mastrovito multiplier and a high-speed delay-driven tree architecture for the second block of Mastrovito multiplier are employed in the new circuit. Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are also calculated for many fields used in Reed-Solomon codes applications and compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2^m) field. The effectiveness of the proposed solution in a real application is verified by implementing in a 0.25?m CMOS technology the key equation solving block of a (255,239) Reed-Solomon decoder. The use of the proposed multiplier in this application results in a substantial speed improvement without any penalty in silicon area occupation.</p>
<b>Index Terms</b>—VLSI, Arithmetic, Digital, High-Performance, finite field multiplication, Reed-Solomon codes, polynomial basis

A. G. Strollo, D. D. Caro and N. Petra, "A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme," in IEEE Transactions on Computers, vol. 56, no. , pp. 1470-1483, 2007.
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